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參數(shù)資料
| 型號(hào)： | M80C186 |
| 廠商： | Intel Corp. |
| 英文描述： | CHMOS HIGH INTEGRATION 16-BIT MICROPROCESSOR |
| 中文描述： | CHMOS高集成16位微處理器 |
| 文件頁數(shù)： | 34/59頁 |
| 文件大小： | 590K |
| 代理商： | M80C186 |
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M80C186
M80C186 CPU. In the edge-sense mode, if the level
remains high after the interrupt is acknowledged, the
input is disabled and no further requests will be gen-
erated. The input level must go LOW for at least one
clock cycle to reenable the input. In the level-trigger
mode, no such provision is made: holding the inter-
rupt input HIGH will cause continuous interrupt re-
quests.
Interrupt Vectoring
The M80C186 Interrupt Controller will generate in-
terrupt vectors for the integrated DMA channels and
the integrated Timers. In addition, the Interrupt Con-
troller will generate interrupt vectors for the external
interrupt lines if they are not configured in Cascade
or Special Fully Nested Mode. The interrupt vectors
generated are fixed and cannot be changed (see Ta-
ble 4).
Interrupt Controller Registers
The Interrupt Controller register model is shown in
Figure 24. It contains 15 registers. All registers can
both be read or written unless specified otherwise.
In-Service Register
This register can be read from or written into. The
format is shown in Figure 25. It contains the In-Serv-
ice bit for each of the interrupt sources. The In-Serv-
ice bit is set to indicate that a source’s service rou-
tine is in progress. When an In-Service bit is set, the
interrupt controller will not generate interrupts to the
CPU when it receives interrupt requests from devic-
es with a lower programmed priority level. The TMR
bit is the In-Service bit for all three timers; the D0
and D1 bits are the In-Service bits for the two DMA
channels; the I0–I3 are the In-Service bits for the
external interrupt pins. The IS bit is set when the
processor acknowledges an interrupt request either
by an interrupt acknowledge or by reading the poll
register. The IS bit is reset at the end of the interrupt
service routine by an end-of-interrupt command is-
sued by the CPU.
Interrupt Request Register
The internal interrupt sources have interrupt request
bits inside the interrupt controller. The format of this
register is shown in Figure 25. A read from this regis-
ter yields the status of these bits. The TMR bit is the
logical OR of all timer interrupt requests. D0 and D1
are the interrupt request bits for the DMA channels.
The state of the external interrupt input pins is also
indicated. The state of the external interrupt pins is
not a stored condition inside the interrupt controller,
therefore the external interrupt bits cannot be writ-
ten. The external interrupt request bits show exactly
when an interrupt request is given to the interrupt
controller, so if edge-triggered mode is selected, the
bit in the register will be HIGH only after an inactive-
to-active transition. For internal interrupt sources,
the register bits are set when a request arrives and
are reset when the processor acknowledges the re-
quests.
Writes to the interrupt request register will affect the
D0 and D1 interrupt request bits. Setting either bit
will cause the corresponding interrupt request while
clearing either bit will remove the corresponding in-
terrupt request. All other bits in the register are read-
only.
Mask Register
This is a 16-bit register that contains a mask bit for
each interrupt source. The format for this register is
shown in Figure 25. A one in a bit position corre-
270500–12
Figure 23. Cascade and Special Fully Nested Mode Interrupt Controller Connections
34
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