參數(shù)資料
型號(hào)： M80287
廠商： Intel Corp.
英文描述： 80-BIT HMOS* NUMERIC PROCESSOR EXTENSION
中文描述： 80位的保健組織*數(shù)值處理器擴(kuò)展
文件頁(yè)數(shù)： 2/24頁(yè)
文件大小： 399K
代理商： M80287
M80287
Table 1. M80287 Pin Description
Symbol
Type
Name and Function
CLK
I
CLOCK INPUT:
This clock provides the basic timing for internal M80287
operations. Special MOS level inputs are required. The M82284 or M8284A
CLK outputs are compatible to this input.
CKM
I
CLOCK MODE SIGNAL:
Indicates whether CLK input is to be divided by 3
or used directly. A HIGH input will select the latter option. This input may be
connected to V
CC
or V
SS
as appropriate. This input must be either HIGH or
LOW 20 CLK cycles before RESET goes LOW.
RESET
I
SYSTEM RESET:
Causes the M80287 to immediately terminate its present
activity and enter a dormant state. RESET is required to be HIGH for more
than 4 M80287 CLK cycles. For proper initialization the HIGH-LOW
transition must occur no sooner than 50
m
s after V
CC
and CLK meet their
D.C. and A.C. specifications.
D15–D0
I/O
DATA:
16-bit bidirectional data bus. Inputs to these pins may be applied
asynchronous to the M80287 clock.
BUSY
O
BUSY STATUS:
Asserted by the M80287 to indicate that it is currently
executing a command.
ERROR
O
ERROR STATUS:
Reflects the ES bit of the status word. This signal
indicates that an unmasked error condition exists.
PEREQ
O
PROCESSOR EXTENSION DATA CHANNEL OPERAND TRANSFER
REQUEST:
A HIGH on this output indicates that the M80287 is ready to
transfer data. PEREQ will be disabled upon assertion of PEACK or upon
actual data transfer, whichever occurs first, if no more transfers are required.
PEACK
I
PROCESSOR EXTENSION DATA CHANNEL OPERAND TRANSFER
ACKNOWLEDGE:
Acknowledges that the request signal (PEREQ) has been
recognized. Will cause the request (PEREQ) to be withdrawn in case there
are no more transfers required. PEACK may be asynchronous to the
M80287 clock.
NPRD
I
NUMERIC PROCESSOR READ:
Enables transfer of data from the M80287.
This input may be asynchronous to the M80287 clock.
NPWR
I
NUMERIC PROCESSOR WRITE:
Enables transfer of data to the M80287.
This input may be asynchronous to the M80287 clock.
NPS1, NPS2
I
NUMERIC PROCESSOR SELECTS:
Indicates the CPU is performing an
ESCAPE instruction. Concurrent assertion of these signals (i.e., NPS1 is
LOW and NPS2 is HIGH) enables the M80287 to perform floating point
instructions. No data transfers involving the M80287 will occur unless the
device is selected via these lines. These inputs may be asynchronous to the
M80287 clock.
CMD1, CMD0
I
COMMAND LINES:
These, along with select inputs, allow the CPU to direct
the operation of the M80287. No actions will occur if these signals are both
HIGH. These inputs may be asynchronous to the M80287 clock.
CLK286
I
CPU CLOCK:
This input provides a sampling edge for the M80287 inputs
S1, S0, COD/INTA, READY, and HLDA. It must be connected to the
M80286 CLK input.
S1, S0
COD/INTA
I
STATUS:
These inputs allow the M80287 to monitor the execution of
ESCAPE instructions by the M80286. They must be connected to the
corresponding M80286 pins.
HLDA
I
HOLD ACKNOWLEDGE:
This input informs the M80287 when the M80286
controls the local bus. It must be connected to the M80286 HLDA output.
READY
I
READY:
The end of a bus cycle is signaled by this input. It must be
connected to the M80286 READY input.
V
SS
V
CC
I
GROUND:
System ground, both pins must be connected to ground.
POWER:
a
5V supply.
I
2
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