參數(shù)資料
型號: M80287
廠商: Intel Corp.
英文描述: 80-BIT HMOS* NUMERIC PROCESSOR EXTENSION
中文描述: 80位的保健組織*數(shù)值處理器擴(kuò)展
文件頁數(shù): 17/24頁
文件大小: 399K
代理商: M80287
M80287
Bits 14–12 of the status word point to the M80287
register that is the current top-of-stack (TOP) as de-
scribed above. Figure 6 shows the six error flags in
bits 5–0 of the status word. Bits 5–0 are set to indi-
cate that the NEU has detected an exception while
executing an instruction. The section on exception
handling explains how they are set and used.
Bit 7 is the error status bit. This bit is set if any un-
masked exception bit is set and cleared otherwise. If
this bit is set, the ERROR signal is asserted.
Tag Word
The tag word marks the content of each register as
shown in Figure 7. The principal function of the tag
word is to optimize the NPX’s performance. The tag
word can be used, however, to interpret the con-
tents of M80287 registers.
Instruction and Data Pointers
The instruction and data pointers (see Figures 8a
and 8b) are provided for user-written error handlers.
Whenever the M80287 executes a new instruction,
the BIU saves the instruction address, the operand
address (if present) and the instruction opcode.
M80287 instructions can store this data into memo-
ry.
The instruction and data pointers appear in one of
two formats depending on the operating mode of the
M80287. In real mode, these values are the 20-bit
physical address and 11-bit opcode formatted like
the M8087. In protected mode, these values are the
32-bit virtual addresses used by the program which
executed an ESC instruction. The same FLDENV/
FSTENV/FSAVE/FRSTOR instructions as those of
the M8087 are used to transfer these values be-
tween the M80287 registers and memory.
Table 5a. Condition Code Interpretation
Instruction
Type
C
3
C
2
C
1
C
0
Interpretation
Compare, Test
0
0
1
1
0
0
0
1
X
X
X
X
0
1
0
1
ST
l
Source or 0 (FTST)
ST
k
Source or 0 (FTST)
ST
e
Source or 0 (FTST)
ST is not comparable
Remainder
Q
1
0
Q
0
Q
2
Complete reduction with
three low bits of quotient
(See Table 5b)
Incomplete Reduction
U
1
U
U
Examine
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Valid, positive unnormalized
Invalid, positive, exponent
e
0
Valid, negative, unnormalized
Invalid, negative, exponent
e
0
Valid, positive, normalized
Infinity, positive
Valid, negative, normalized
Infinity, negative
Zero, positive
Empty
Zero, negative
Empty
Invalid, positive, exponent
e
0
Empty
Invalid, negative, exponent
e
0
Empty
NOTES:
1. ST
e
Top of stack
2. X
e
value is not affected by instruction
3. U
e
value is undefined following instruction
4. Q
n
e
Quotient bit n
17
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