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參數(shù)資料
| 型號(hào)： | M80287 |
| 廠商： | Intel Corp. |
| 英文描述： | 80-BIT HMOS* NUMERIC PROCESSOR EXTENSION |
| 中文描述： | 80位的保健組織*數(shù)值處理器擴(kuò)展 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 399K |
| 代理商： | M80287 |
M80287
Table 3. Execution Time for Selected M80287 Instructions
Approximate Execution
Time (
m
s)
Floating Point Instruction
M80287
(5 MHz Operation)
Add/Subtract
14/18
Multiply (Single Precision)
19
Multiply (Extended Precision)
27
Divide
39
Compare
9
Load (Double Precision)
10
Store (Double Precision)
21
Square Root
36
Tangent
90
Exponentiation
100
INTERRUPT DESCRIPTION
Several interrupts of the M80286 are used to report
exceptional conditions while executing numeric pro-
grams in either real or protected mode. The inter-
rupts and their functions are shown in Table 4.
PROCESSOR ARCHITECTURE
As shown in Figure 1, the NPX is internally divided
into two processing elements, the bus interface unit
(BIU) and the numeric execution unit (NEU). The
NEU executes all numeric instructions, while the BIU
receives and decodes instructions, requests oper-
and transfers to and from memory and executes
processor control instructions. The two units are
able to operate independently of one another allow-
ing the BIU to maintain asynchronous communica-
tion with the CPU while the NEU is busy processing
a numeric instruction.
BUS INTERFACE UNIT
The BIU decodes the ESC instruction executed by
the CPU. If the ESC code defines a math instruction,
the BIU transmits the formatted instruction to the
NEU. If the ESC code defines an administrative in-
struction, the BIU executes it independently of the
NEU. The parallel operation of the NPX with the
CPU is normally transparent to the user. The BIU
generates the BUSY and ERROR signals for
M80286/M80287 processor synchronization, and
error notification, respectively.
The M80287 executes a single numeric instruction
at a time. When executing most ESC instructions,
the M80286 tests the BUSY pin and waits until the
M80287 indicates that it is not busy before initiating
the command. Once initiated, the M80286 continues
program execution while the M80287 executes the
ESC instruction. In M8086/20 systems, this synchro-
nization is achieved by placing a WAIT instruction
before an ESC instruction. For most ESC instruc-
tions, the M80286/20 does not require a WAIT in-
struction before the ESC opcode. However, the
M80286/20 will operate correctly with these WAIT
instructions. In all cases, a WAIT or ESC instruction
should be inserted after any M80287 store to memo-
ry (except FSTSW and FSTCW) or load from memo-
ry (except FLDENV or FRSTOR) before the M80286
reads or changes the value.
Data transfers between memory and the M80287,
when needed, are controlled by the PEREQ,
PEACK, NPRD, NPWR, NPS1, NPS2 signals. The
M80286 does the actual data transfer with memory
through its processor extension data channel. Nu-
meric data transfers with memory performed by the
M80286 use the same timing as any other bus cycle.
Control signals for the M80287 are generated by the
M80286 as shown in Figure 4, and meet the timing
requirements shown in the AC requirements section.
14
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