參數(shù)資料
型號: M80287
廠商: Intel Corp.
英文描述: 80-BIT HMOS* NUMERIC PROCESSOR EXTENSION
中文描述: 80位的保健組織*數(shù)值處理器擴(kuò)展
文件頁數(shù): 15/24頁
文件大?。?/td> 399K
代理商: M80287
M80287
Table 4. Interrupt Vectors
Interrupt Number
Interrupt Function
7
An ESC instruction was encountered when EM or TS of the M80286 MSW was
set. EM
e
1 indicates that software emulation of the instruction is required. When
TS is set, either an ESC or WAIT instruction will cause interrupt 7. This indicates
that the current NPX context may not belong to the current task.
9
The second or subsequent words of a numeric operand in memory exceeded a
segment’s limit. This interrupt occurs after executing an ESC instruction. The
saved return address will not point at the numeric instruction causing this interrupt.
After processing the addressing error, the M80286 program can be restarted at
the return address with IRET. The address of the failing numeric instruction and
numeric operand are saved in the M80287. An interrupt handler for this interrupt
must execute FNINIT beforeany other ESC or WAIT instruction.
13
The starting address of a numeric operand is not in the segment’s limit. The return
address will point at the ESC instruction (including prefixes) causing this error. The
M80287 has not executed this instruction. The instruction and data address in
M80287 refer to a previous, correctly executed, instruction.
16
The previous numeric instruction caused an unmasked numeric error. The
address of the faulty numeric instruction or numeric data operand is stored in the
M80287. Only ESC or WAIT instructions can cause this interrupt. The M80286
return address will point at a WAIT or ESC instruction, including prefixes, which
may be restarted after clearing the error condition in the NPX.
NUMERIC EXECUTION UNIT
The NEU executes all instructions that involve the
register stack; these include arithmetic, logical, tran-
scendental, constant and data transfer instructions.
The data path in the NEU is 84 bits wide (68 fraction
bits, 15 exponent bits and a sign bit) which allows
internal operand transfers to be performed at very
high speeds.
When the NEU begins executing an instruction, it
activates the BIU BUSY signal. This signal is used in
conjunction with the CPU WAIT instruction or auto-
matically with most of the ESC instructions to syn-
chronize both processors.
REGISTER SET
The M80287 register set is shown in Figure 5. Each
of the eight data registers in the M8087’s register
stack is 80 bits wide and is divided into ‘‘fields’’ cor-
responding to the NPX’s temporary real data type.
At a given point in time the TOP field in the status
word identifies the current top-of-stack register. A
‘‘push’’ operation decrements TOP by 1 and loads a
value into the new top register. A ‘‘pop’’ operation
stores the value from the current top register and
then increments TOP by 1. Like M80286 stacks in
memory, the M80287 register stack grows ‘‘down’’
toward lower-addressed registers.
Instructions may address the data registers either
implicitly or explicitly. Many instructions operate on
the register at the top of the stack. These instruc-
tions implicitly address the register pointed by the
TOP. Other instructions allow the programmer to ex-
plicitly specify the register which is to be used. Ex-
plicit register addressing is ‘‘top-relative.’’
Status Word
The 16-bit status word (in the status register) shown
in Figure 6 reflects the overall state of the M80287.
It may be read and inspected by CPU code. The
busy bit (bit 15) indicates whether the NEU is exe-
cuting an instruction (B
e
1) or is idle (B
e
0).
The instructions FSTSW, FSTENV, FSTSWAX and
FSAVE which store the status word are executed
exclusively by the BIU and do not set the busy bit
themselves or require the Busy bit be cleared in or-
der to be executed.
The four numeric condition code bits (C
0
–C
3
) are
similar to the flags in a CPU: instructions that per-
form arithmetic operations update these bits to re-
flect the outcome of NDP operations. The effect of
these instructions on the condition code bits is sum-
marized in Tables 5a and 5b.
15
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