- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359084 > M59BW10225N1T (意法半導(dǎo)體) 1 Mbit 64Kb x16, Burst Low Voltage Flash Memory PDF資料下載
參數(shù)資料
| 型號(hào)： | M59BW10225N1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 1 Mbit 64Kb x16, Burst Low Voltage Flash Memory |
| 中文描述： | 1兆位64Kb的x16插槽，突發(fā)低電壓快閃記憶體 |
| 文件頁(yè)數(shù)： | 9/24頁(yè) |
| 文件大?。?/td> | 181K |
| 代理商： | M59BW10225N1T |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)當(dāng)前第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)
9/24
M59BW102
Figure 6. AC Testing Load Circuit
AI01119
1.3V
OUT
CL = 30pF
CL includes JIG capacitance
3.3k
1N914
DEVICE
UNDER
TEST
Table 9. AC Measurement Conditions
Load Capacitance (C
L
)
30pF
Input Rise and Fall Times
≤
10ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Figure 5. AC Testing Input Output Waveform
AI01417
3V
0V
1.5V
Table 10. Capacitance
(1)
(T
A
= 25 °C, f = 1 MHz)
Symbol
Parameter
Note: 1. Sampled only, not 100% tested.
Test Condition
Min
Max
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
12
pF
ten to address 555h on the third cycle after the two
Coded cycles. The Chip Erase Confirm command
10h is similarly written on the sixth cycle after an-
other two Coded cycles. If the second command
given is not an erase confirm or if the Coded cy-
cles are wrong, the instruction aborts and the de-
vice is reset to Read Array. It is not necessary to
program the array with 0000h first as the P/E.C.
will automatically do this before erasing it to
FFFFh. Read operations after the sixth rising edge
of W or E output the Status Register bits. During
the execution of the erase by the P/E.C., Data
Polling bit DQ7 returns '0', then '1' on completion.
The Toggle bits DQ2 and DQ6 toggle during erase
operation and stop when erase is completed. After
completion the Status Register bit DQ5 returns '1'
if there has been an Erase Failure.
POWER SUPPLY
Power Up
The memory Command Interface is reset on pow-
er up to Read Array. Either E or W must be tied to
V
IH
during Power Up to allow maximum security
and the possibility to write a command on the first
rising edge of E and W. Any write cycle initiation is
blocked when V
CC
is below V
LKO
.
Supply Rails
Normal precautions must be taken for supply volt-
age decoupling; each device in a system should
have the V
CC
rail decoupled with a 0.1μF capacitor
close to the V
CC
and V
SS
pins. The PCB trace
widths should be sufficient to carry the V
CC
pro-
gram and erase currents required.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M59BW102N | 1 Mbit 64Kb x16, Burst Low Voltage Flash Memory |
| M59DR008 | 8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
| M59DR008E100N1T | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TV07; No. of Contacts:56; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Jam Nut Receptacle; Body Style:Straight |
| M59DR008E100N6T | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TV07; Number of Contacts:56; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Jam Nut Receptacle; Body Style:Straight |
| M59DR008E100ZB1T | 8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M59BW102N | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 64Kb x16, Burst Low Voltage Flash Memory |
| M59DR008 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
| M59DR008E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
| M59DR008E100N1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
| M59DR008E100N6T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。