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參數(shù)資料
| 型號(hào)： | M59BW10225N1T |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 1 Mbit 64Kb x16, Burst Low Voltage Flash Memory |
| 中文描述： | 1兆位64Kb的x16插槽，突發(fā)低電壓快閃記憶體 |
| 文件頁(yè)數(shù)： | 2/24頁(yè) |
| 文件大小： | 181K |
| 代理商： | M59BW10225N1T |
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M59BW102
2/24
Figure 2. TSOP Connections
DQ6
DQ7
VSS
DQ3
DQ4
DQ2
DQ13
DQ12
DQ8
DQ10
DQ9
A14
A15
ALE
A8
A7
A6
A5
A11
A12
A10
A4
A3
A9
G
DQ0
A2
A1
DQ1
A0
W
E
DQ14
NC
VCC
DQ15
AI02764B
M59BW102
10
11
1
20
21
30
31
40
A13
DQ11
DQ5
VSS
Command Interface
Instructions, made up of commands written in cy-
cles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and
fifth cycles are used to input Coded cycles to the
C.I. This Coded sequence is the same for all Pro-
gram/Erase Controller instructions. The ’Com-
mand’ itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrect command or any improper command se-
quence will reset the device to Read Array mode.
Instructions
Four instructions are defined to perform Read Ar-
ray, Auto Select (to read the Electronic Signature),
Program, Chip Erase. The internal P/E.C. auto-
matically handles all timing and verification of the
Program and Erase operations. The Status Regis-
ter Data Polling, Toggle and Error bits may be read
at any time, during programming or erase, to mon-
itor the progress of the operation.
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
Command Interface which is common to all in-
structions (see Table 7). The third cycle inputs the
instruction set-up command. Subsequent cycles
output the addressed data or Electronic Signature
for Read operations. In order to give additional
data protection, the instructions for Program and
Chip Erase require further command inputs. For a
Program instruction, the fourth command cycle in-
puts the address and data to be programmed. For
an Erase instruction, the fourth and fifth cycles in-
put a further Coded sequence before the com-
mand confirmation on the sixth cycle.
Table 1. Signal Names
A0-A15
Address Inputs
DQ0-DQ7
Data Inputs/Outputs, Command Inputs
DQ8-DQ15
Data Inputs/Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
ALE
Address Latch Enable
V
CC
Supply Voltage
V
SS
Ground
NC
Not Connected Internally
Organization
The M59BW102 is organized as 64K x16 bits. The
memory uses the address inputs A0-A15 and the
Data Inputs/Outputs DQ0-DQ15. Memory control
is provided by Chip Enable E, Output Enable G,
Address Latch Enable ALE and Write Enable W in-
puts.
Erase and Program operations are controlled by
an internal Program/Erase Controller (P/E.C.).
Status Register data output on DQ7 provides a
Data Polling signal, and DQ6 and DQ2 provide
Toggle signals to indicate the state of the P/E.C
operations.
Bus Operations
The following operations can be performed using
the appropriate bus cycles: Read (Array, Electron-
ic Signature), Write command, Output Disable,
Standby. See Tables 3 and 4.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M59BW102N | 1 Mbit 64Kb x16, Burst Low Voltage Flash Memory |
| M59DR008 | 8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
| M59DR008E100N1T | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TV07; No. of Contacts:56; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Jam Nut Receptacle; Body Style:Straight |
| M59DR008E100N6T | Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TV07; Number of Contacts:56; Connector Shell Size:25; Connecting Termination:Crimp; Circular Shell Style:Jam Nut Receptacle; Body Style:Straight |
| M59DR008E100ZB1T | 8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M59BW102N | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:1 Mbit 64Kb x16, Burst Low Voltage Flash Memory |
| M59DR008 | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
| M59DR008E | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
| M59DR008E100N1T | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
| M59DR008E100N6T | 制造商:STMICROELECTRONICS 制造商全稱(chēng):STMicroelectronics 功能描述:8 Mbit 512Kb x16, Dual Bank, Page Low Voltage Flash Memory |
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