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參數(shù)資料
| 型號： | M48T513V-70CS1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO32 |
| 封裝： | 10 X 20 MM, PLASTIC, TSOP2-32 |
| 文件頁數(shù)： | 3/30頁 |
| 文件大?。?/td> | 161K |
| 代理商： | M48T513V-70CS1 |
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M48T513Y, M48T513V
Table 4. Write Mode AC Characteristics
Note: 1. CL = 5pF.
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
Data Retention Mode
With valid VCC applied, the M48T513Y/V operates
as a conventional BYTEWIDE static RAM. Should
the supply voltage decay, the RAM will automati-
cally deselect, write protecting itself when VCC
falls between VPFD (max), VPFD (min) window. All
outputs become high impedance and all inputs are
treated as ”don’t care.”
Note: A power failure during a write cycle may cor-
rupt data at the current addressed location, but
does not jeopardize the rest of the RAM’s content.
At voltages below VPFD (min), the memory will be
in a write protected state, provided the VCC fall
time is not less than tF. The M48T513Y/V may re-
spond to transient noise spikes on VCC that cross
into the deselect window during the time the de-
vice is sampling VCC. Therefore, decoupling of the
power supply lines is recommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery, preserving
data and powering the clock. The internal energy
source will maintain data in the M48T513Y/V for
an accumulated period of at least 10 years at room
temperature. As system power rises above VSO,
the battery is disconnected, and the power supply
is switched to external VCC. Deselect continues for
tREC after VCC reaches VPFD (max). For a further
more detailed review of lifetime calculations,
please see Application Note AN1012.
Symbol
Parameter
M48T513Y
M48T513Y/M48T513V
Unit
-70
-85
Min
Max
Min
Max
tAVAV
Write Cycle Time
70
85
ns
tAVWL
Address Valid to Write Enable Low
0
ns
tAVEL
Address Valid to Chip Enable Low
0
ns
tWLWH
Write Enable Pulse Width
50
60
ns
tELEH
Chip Enable Low to Chip Enable High
55
65
ns
tWHAX
Write Enable High to Address Transition
5
ns
tEHAX
Chip Enable High to Address Transition
10
15
ns
tDVWH
Input Valid to Write Enable High
30
35
ns
tDVEH
Input Valid to Chip Enable High
30
35
ns
tWHDX
Write Enable High to Input Transition
5
ns
tEHDX
Chip Enable High to Input Transition
10
15
ns
tWLQZ
(1, 2)
Write Enable Low to Output Hi-Z
25
30
ns
tAVWH
Address Valid to Write Enable High
60
70
ns
tAVEH
Address Valid to Chip Enable High
60
70
ns
tWHQX
(1, 2)
Write Enable High to Output Transition
5
ns
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M48T513V-70PM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| M48T513V-85CS1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| M48T513V-85PM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| M48T513VPM | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
| M48T513VSH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 4 Mbit 512Kb x8 TIMEKEEPER SRAM |
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