
M48T513Y, M48T513V
4/30
DESCRIPTION
The M48T513Y/V TIMEKEEPER RAM is a 512Kb
x 8 non-volatile static RAM and real time clock,
with programmable alarms and a watchdog timer.
The special DIP package provides a fully integrat-
ed battery back-up memory and real time clock so-
lution. The M48T513Y/V directly replaces industry
standard 512Kb x 8 SRAM. It also provides the
non-volatility of Flash without any requirement for
special write timing or limitations on the number of
writes that can be performed.
For surface mount environments ST provides a
Chip Set solution consisting of a 44 pin 330mil
SOIC TIMEKEEPER Supervisor (M48T201V/Y)
and a 32 pin TSOP Type II (10 x 20mm) LPSRAM
(M68Z512/W) packages.
The 44 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery.
The unique design allows the SNAPHAT battery
package to be mounted on top of the SOIC pack-
age after the completion of the surface mount pro-
cess. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
The SNAPHAT battery package is shipped sepa-
rately in plastic anti-static tubes or in Tape & Reel
form. The part number is ”M4Txx-BR12SH1”.
Figure 5, page 6 illustrates the static memory array
and the quartz controlled clock oscillator. The
clock locations contain the century, year, month,
date, day, hour, minute, and second in 24 hour
BCD format. Corrections for 28, 29 (leap year), 30,
and 31 day months are made automatically. The
nine clock bytes (7FFFFh-7FFF9h and 7FFF1h)
are not the actual clock counters, they are memory
locations consisting of BiPORT
read/write mem-
ory cells within the static RAM array.
The M48T513Y/V includes a clock control circuit
which updates the clock bytes with current infor-
mation once per second. The information can be
accessed by the user in the same manner as any
other location in the static memory array. Byte
7FFF8h is the clock control register. This byte con-
trols user access to the clock information and also
stores the clock calibration setting.
Byte 7FFF7h contains the watchdog timer setting.
The watchdog timer can generate either a reset or
an interrupt, depending on the state of the Watch-
dog Steering bit (WDS). Bytes 7FFF6h-7FFF2h in-
clude bits that, when programmed, provide for
clock alarm functionality. Alarms are activated
when the register content matches the month,
date, hours, minutes, and seconds of the clock
registers. Byte 7FFF1h contains century informa-
tion. Byte 7FFF0h contains additional flag informa-
tion pertaining to the watchdog timer, the alarm
condition and the battery status. The M48T513Y/V
also has its own Power-Fail Detect circuit. This
control circuitry constantly monitors the supply
voltage for an out of tolerance condition. When
VCC is out of tolerance, the circuit write protects
the TIMEKEEPER register data and external
SRAM, providing data security in the midst of un-
predictable system operation. As VCC falls, the
control circuitry automatically switches to the bat-
tery, maintaining data and clock operation until
valid power is restored.