參數(shù)資料
型號: M48T513V-70CS1
廠商: STMICROELECTRONICS
元件分類: 時鐘/數(shù)據(jù)恢復(fù)及定時提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO32
封裝: 10 X 20 MM, PLASTIC, TSOP2-32
文件頁數(shù): 29/30頁
文件大?。?/td> 161K
代理商: M48T513V-70CS1
M48T513Y, M48T513V
8/30
OPERATING MODES
Read Mode
The M48T513Y/V is in the Read Mode whenever
W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 Ad-
dress Inputs defines which one of the 524,272
bytes of data is to be accessed. Valid data will be
available at the Data I/O pins within tAVQV (Ad-
dress Access Time) after the last address input
signal is stable, providing the E and G access
times are also satisfied. If the E and G access
times are not met, valid data will be available after
the latter of the Chip Enable Access Times (tELQV)
or
Output
Enable
Access
Time
(tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for tAXQX (Output
Data Hold Time) but will go indeterminate until the
next Address Access.
Table 2. Operating Modes
Note: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
2. See Table 11, page 21 for details.
Figure 7. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
Mode
VCC
E
G
W
DQ0-DQ7
Power
Deselect
4.5 to 5.5V
or
3.0 to 3.6V
VIH
X
High Z
Standby
Write
VIL
X
VIL
DIN
Active
Read
VIL
VIH
DOUT
Active
Read
VIL
VIH
High Z
Active
Deselect
VSO to VPFD (min)
(2)
X
High Z
CMOS Standby
Deselect
≤ VSO (2)
X
High Z
Battery Back-up Mode
AI01197
tAVAV
tAVQV
tAXQX
tELQV
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
DATA OUT
A0-A16
E
G
DQ0-DQ7
VALID
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