參數(shù)資料
型號(hào)： M44C890-H
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Low-Current Microcontroller for Wireless Communication
中文描述： 4-BIT, EEPROM, MICROCONTROLLER, PDSO20
封裝： SSO-20
文件頁(yè)數(shù)： 37/63頁(yè)
文件大?。?/td> 503K
代理商： M44C890-H
M44C890
M44C090
Rev.A4, 14-Dec-01
37 (63)
Timer 2 Compare and Compare Mode Registers
Timer 2 has two separate compare registers, T2CO1 for
the 4-bit stage and T2CO2 for the 8-bit stage of Timer 2.
The timer compares the contents of the compare register
current counter value and if it matches it generates an
output signal. Dependent on the timer mode, this signal
is used to generate a timer interrupt, to toggle the output
flip-flop as SSI clock or as a clock for the next counter
stage.
In the 12-bit timer mode, T2CO1 contains bits 0 to 3 and
T2CO2 bits 4 to 11 of the 12-bit compare value. In all
other modes, the two compare registers work
independently as a 4- and 8-bit compare register. When
assigned to the compare register a compare event will be
supressed.
Timer 2 Compare Mode Register (T2CM)
Address:
’
7
’
hex
–
Subaddress:
’
3
’
hex
Bit 3
Bit 2
Bit 1
Bit 0
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áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
T
imer
2
O
verflow
T
oggle
M
ask bit
If the T2OTM-bit is set, only a counter overflow can generate an interrupt except on
the Timer 2 output mode 7.
T
imer
2
C
ompare
T
oggle
M
ask bit
put flip-flop (TOG2). In Timer 2 output mode 7 and when the T2CTM-bit is set, only
a match of the counter with the compare register can generate an interrupt.
T
imer
2
R
eset
M
ask bit
disable counter reset
enable counter reset, a match of the counter with the compare register resets the
counter
T
imer
2
I
nterrupt
M
ask bit
disable Timer 2 interrupt
T2OTM
Timer 2 Output Mode
T2OTM
1, 2, 3, 4, 5 and 6
0
1, 2, 3, 4, 5 and 6
1
7
x
á
á
á
á
áááááááááááááááááááááááááááááááá
T2CTM
áááááááááááááááááááááááááááááááá
T2IM
áááááááááááááááááááááááááááááááá
T2CTM
x
x
1
Timer 2 Interrupt Source
Compare match (CM2)
Overflow (OVF2)
Compare match (CM2)
Timer 2 COmpare Register 1 (T2CO1)
Address:
’
7
’
hex
–
Subaddress:
’
4
’
hex
áááááááááááááááááááááááááááááááá
In prescaler mode the clock is bypassed if the compare register T2CO1 contains 0.
Bit 0
áááááááááááááááááááááááááááááááá
Timer 2 COmpare Register 2 (T2CO2) Byte Write
Address:
’
7
’
hex
–
Subaddress:
’
5
’
hex
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
Second write cycle
Bit 7
Bit 6
Bit 5
Bit 0
Bit 4
áááááááááááááááááááááááááááááááá
Reset value: 1111b
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