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參數(shù)資料
| 型號： | M44C890-H |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low-Current Microcontroller for Wireless Communication |
| 中文描述： | 4-BIT, EEPROM, MICROCONTROLLER, PDSO20 |
| 封裝： | SSO-20 |
| 文件頁數(shù)： | 22/63頁 |
| 文件大?。?/td> | 503K |
| 代理商： | M44C890-H |
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M44C890
M44C090
Rev.A4, 14-Dec-01
22 (63)
3.2.2
Bidirectional Port 5
This, and all other bidirectional ports include a bitwise
programmable Control Register (P5CR), which allows
the individual programming of each port bit as input or
output. It also opens up the possibility of reading the pin
condition when in output mode. This is a useful feature
for self testing and for serial bus applications.
The port pins can also be used as external interrupt inputs
(see figures 24 & 25). The interrupts (INT1 and INT6) can
be masked or independently configured to trigger on ei-
ther edge. The interrupt configuration and port direction
is controlled by the Port 5 Control Register (P5CR). An
additional low resistance pull
–
up/
–
down transistor mask
option provides an internal bus pull
–
up for serial bus ap-
plications.
The Port 5 Data Register (P5DAT) is I/O mapped to the
primary address register of address
’
5
’
h and the Port 5
Control Register (P5CR) to the corresponding auxiliary
register. The P5CR is a byte-wide register and is config-
ured by writing first the low nibble then the high nibble
(see section 2.1
”
Addressing peripherals
”
).
Master reset
Q
VDD
BP5y
Mask options
*
*
P5DATy
I/O Bus
D
IN enable
I/O Bus
*
*
Pull-up
Pull-down
VDD
*
Static
Pull-up
(Data out)
S
*
VDD
Static
Pull-down
Switched
Switched
Figure 23. Bidirectional Port 5
Bidir. Port
Data in
IN_Enable
BP53
P53M2 P53M1 P52M2 P52M1 P51M2 P51M1 P50M2 P50M1
Decoder
Decoder
Decoder
Decoder
Bidir. Port
Data in
IN_Enable
BP52
I/O
–
bus
Bidir. Port
Data in
IN_Enable
BP51
I/O
–
bus
Bidir. Port
Data in
IN_Enable
BP50
INT1
INT6
P5CR:
13764
Figure 24. Port 5 external interrupts
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