參數(shù)資料
型號： M44C890-H
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Low-Current Microcontroller for Wireless Communication
中文描述： 4-BIT, EEPROM, MICROCONTROLLER, PDSO20
封裝： SSO-20
文件頁數(shù)： 17/63頁
文件大?。?/td> 503K
代理商： M44C890-H
M44C890
M44C090
Rev.A4, 14-Dec-01
17 (63)
4
–
MHz
oscillator
4Out
4Out
OSC1
OSC2
Oscin
Oscout
XTAL
4 MHz
Stop
Osc
–
Stop
Figure 18. 4-MHz crystal oscillator
4
–
MHz
oscillator
4Out
Stop
4Out
Osc
–
Stop
OSC1
OSC2
Oscin
C2 = C3 = 22 pF
Oscout
Cer.
Res
C3
C4
4 MHz
Figure 19. Ceramic resonator
32-kHz Oscillator
Some applications require long-term time keeping or low
resolution timing. In this case, an on
–
chip, low power
32-kHz crystal oscillator can be used to generate both the
SUBCL and the SYSCL. In this mode, power
consumption is greatly reduced. The 32-kHz crystal
oscillator can not be stopped while the power-down mode
is in operation.
32
–
kHz
oscillator
32Out
32Out
OSC1
OSC2
Oscin
Oscout
XTAL
32 kHz
Figure 20. 32-kHz crystal oscillator
2.5.3
Clock Management
The clock management register controls the system clock
divider and synchronization stage. Writing to this register
triggers the synchronization cycle.
Clock Management Register (CM)
Auxiliary register address:
’
3
’
hex
Bit 3
NSTOP
Bit 2
CCS
Bit 1
CSS1
Bit 0
CSS0
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áááááááááááááááááááááááááááááááá
CM:
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
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áááááááááááááááááááááááááááááááá
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ááááááááááááááááááááááá
ááááááááááááááááááááááá
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NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode
NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode
C
ore
C
lock
S
elect
CCS = 1, the internal RC-oscillator 1 generates SYSCL
CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal oscillator, an external clock source or the
internal RC-oscillator 2 with the external resistor at OSC1 generates SYSCL dependent on
the setting of OS0 and OS1 in the system configuration register
C
ore
S
peed
S
elect
0
Reset value: 1111b
CSS1
0
1
1
0
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Note
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