參數(shù)資料
型號： M44C890-H
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Low-Current Microcontroller for Wireless Communication
中文描述： 4-BIT, EEPROM, MICROCONTROLLER, PDSO20
封裝： SSO-20
文件頁數(shù)： 27/63頁
文件大?。?/td> 503K
代理商： M44C890-H
M44C890
M44C090
Rev.A4, 14-Dec-01
27 (63)
Timer 1 Control Register 1 (T1C1)
Address:
’
7
’
hex
–
Subaddress:
’
8
’
hex
Bit 3 *
T1RM
Bit 2
T1C2
Bit 1
T1C1
Bit 0
T1C0
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
T1C1
–
> LSB
Reset value: 1111b
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
The three bits T1C[2:0] select the divider for timer 1. The
resulting time interval depends on this divider and the
timer 1 input clock source. The timer input can be sup-
plied by the system clock, the 32kHz oscillator or via the
clock management. If the clock management generates
the SUBCL, the selected input clock from the RC oscilla-
tor, 4MHz oscillator or an external clock is divided by 16.
T1RM = 1, write access with Timer 1 restart
Note:
if WDL = 0, Timer 1 restart is impossible
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
T1C2
T1C1
T1C0
Divider
Time Interval with
SUBCL
SUBCL / 2
SUBCL / 4
SUBCL / 8
SUBCL / 16
SUBCL / 32
SUBCL / 256
SUBCL / 2048
SUBCL / 16384
Time Interval with
SUBCL = 32 kHz
61
μ
s
122
μ
s
244
μ
s
488
μ
s
0.977 ms
7.812 ms
62.5 ms
500 ms
Time Interval with
SYSCL = 2/1 MHz
1
μ
s / 2
μ
s
2
μ
s / 4
μ
s
4
μ
s / 8
μ
s
8
μ
s / 16
μ
s
16
μ
s / 32
μ
s
128
μ
s / 256
μ
s
1024
μ
s / 2048
μ
s
8192
μ
s / 16384
μ
s
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2
4
8
16
32
256
2048
16384
Timer 1 Control Register 2 (T1C2)
Address:
’
7
’
hex
–
Subaddress:
’
9
’
hex
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
* Bit 3
–
> MSB, Bit 0
–
> LSB
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
áááááááááááááááááááááááááááááááá
T1BP
T1CS = 0, CL1 = SYSCL (see figure 28)
T
imer
1
SUBCL
B
y
P
assed
T1IM
T
imer
1 I
nterrupt
M
ask
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