參數(shù)資料
型號： M44C890-H
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Low-Current Microcontroller for Wireless Communication
中文描述： 4-BIT, EEPROM, MICROCONTROLLER, PDSO20
封裝： SSO-20
文件頁數(shù)： 25/63頁
文件大?。?/td> 503K
代理商： M44C890-H
M44C890
M44C090
Rev.A4, 14-Dec-01
25 (63)
Auxiliary Address:
’
4
’
hex First Write Cycle
Code
3 2 1 0
x x 1 1
x x 1 0
Second Write Cycle
Function
Code
3 2 1 0
x x 1 1
x x 1 0
Function
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
1 1 x x
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
BP41 in intput mode
nal clock input for Timer 2)
1 0 x x
BP42 in input mode
BP43 in output mode
ááááááááááááááááááááááááááááááá
BP42 in output mode
edge interrupt input for INT3)
ááááááááááááááááááááááááááááááá
ááááááááááááááááááááááááááááááá
3.3
The
U
niversal
T
imer/counter/
C
ommunication
M
odule
(UTCM) consists of Timer 1, Timer 2 and a
S
ynchronous
S
erial
I
nterface (SSI).
Universal Timer/Counter / Communication Module (UTCM)
Timer 1 is an interval timer that can be used to
generate periodical interrupts and as prescaler for
Timer 2, the serial interface and the watchdog func-
tion.
Timer 2 is an 8/12-bit timer with an external clock in-
put (T2I) and an output (T2O).
The SSI operates as two wire serial interface or as shift
register for modulation. The modulator units work
together with the timers and shift the data bits out of
the shift register.
There is a multitude of modes in which the timers and the
serial interface can work together.
MUX
Watchdog
Interval / Prescaler
Timer 1
Modu
–
lator 2
4-bit Counter 2/1
Compare 2/1
MUX
MUX DCG
8-bit Counter 2/2
Compare 2/2
Control
Timer 2
MUX
8-bit Shift
–
Register
Receive
–
Buffer
Transmit
–
Buffer
Control
SSI
SCL
INT4
INT2
NRST
INT3
POUT
TOG2
T1OUT
SUBCL
SYSCL
from clock module
13393
T2I
T2O
SC
SD
I/O bus
Figure 26. UTCM block diagram
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