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參數(shù)資料
| 型號： | M44C090 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low-Current Microcontroller for Wireless Communication |
| 中文描述： | 4-BIT, MROM, MICROCONTROLLER, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數(shù)： | 39/63頁 |
| 文件大?。?/td> | 503K |
| 代理商： | M44C090 |
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M44C890
M44C090
Rev.A4, 14-Dec-01
39 (63)
The SSI can generate the shift clock (SC) either from one
of several on-chip clock sources or accept an external
clock. The external shift clock is output on, or applied to
the Port BP40. Selection of an external clock source is
performed by the Serial Clock Direction control bit
(SCD). In the combinational modes, the required clock is
selected by the corresponding timer mode.
The SSI can operate in three data transfer modes
–
synchronous 8-bit shift mode, I
2
C compatible 9-bit shift
modes or 8-bit pseudo I
2
C protocol (without acknowl-
edge-bit).
External SSI clocking is not supported in these modes.
The SSI should thus generate and has full control over the
shift clock so that it can always be regarded as an I
2
C Bus
Master device.
All directional control of the external data port used by
the SSI is handled automatically and is dependent on the
transmission direction set by the Serial Data Direction
(SDD) control bit. This control bit defines whether the
SSI is currently operating in Transmit (TX) mode or
Receive (RX) mode.
Serial data is organized in 8-bit telegrams which are
shifted with the most significant bit first. In the 9-bit I
2
C
mode, an additional acknowledge bit is appended to the
end of the telegram for handshaking purposes (see I
2
C
protocol).
At the beginning of every telegram, the SSI control loads
the transmit buffer into the shift register and proceeds
immediately to shift data serially out. At the same time,
incoming data is shifted into the shift register input. This
incoming data is automatically loaded into the receive
buffer when the complete telegram has been received.
Data can, if required thus be simultaneously received and
transmitted.
Before data can be transferred, the SSI must first be
activated. This is performed by means of the SSI reset
control (SIR) bit. All further operation then depends on
the data directional mode (TX/RX) and the present status
of the SSI buffer registers shown by the Serial Interface
Ready Status Flag (SRDY). This SRDY flag indicates the
(empty/full) status of either the transmit buffer (in TX
mode), or the receive buffer (in RX mode). The control
logic ensures that data shifting is temporarily halted at
any time, if the appropriate receive/transmit buffer is not
ready (SRDY = 0). The SRDY status will then
automatically be set back to
‘
1
’
and data shifting resumed
as soon as the application software loads the new data into
the transmit register (in TX mode) or frees the shift
register by reading it into the receive buffer (in RX mode).
A further activity status (ACT) bit indicates the present
status of the serial communication. The ACT bit remains
high for the duration of the serial telegram or if I
2
C stop
or start conditions are currently being generated. Both the
current SRDY and ACT status can be read in the SSI
status register. To deactivate the SSI, the SIR bit must be
set high.
8-bit Synchronous Mode
In the 8-bit synchronous mode, the SSI can operate as
either a 2 or 3 wire interface (see SSI peripheral
configuration). The serial data (SD) is received or
transmitted in NRZ format, synchronised to either the
rising or falling edge of the shift clock (SC). The choice
of clock edge is defined by the Serial Mode Control bits
(SM0,SM1). It should be noted that
the transmission edge
refers to the SC clock edge with which the SD changes.
To avoid clock skew problems, the incoming serial input
data is shifted in with the opposite edge.
When used together with one of the timer modulator or
demodulator stages, the SSI must be set in the 8-bit
synchronous mode 1.
In RX mode, as soon as the SSI is activated (SIR= 0), 8
shift clocks are generated and the incoming serial data is
shifted into the shift register. This first telegram is
automatically transferred into the receive buffer and the
SRDY set to 0 indicating that the receive buffer contains
valid data. At the same time an interrupt (if enabled) is
generated.
SC
SC
DATA
13823
SD/TO2
1
1
0
1
0
1
0
0
Bit 7
Bit 0
1
1
0
1
0
1
0
0
Bit 7
Bit 0
Data: 00110101
(rising edge)
(falling edge)
Figure 44. 8-bit synchronous mode
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