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參數(shù)資料
| 型號： | M44C090 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low-Current Microcontroller for Wireless Communication |
| 中文描述： | 4-BIT, MROM, MICROCONTROLLER, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數(shù)： | 19/63頁 |
| 文件大?。?/td> | 503K |
| 代理商： | M44C090 |
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M44C890
M44C090
Rev.A4, 14-Dec-01
19 (63)
3
3.1
Peripheral Modules
Addressing Peripherals
Accessing the peripheral modules takes place via the I/O
bus (see figure 21). The IN or OUT instructions allow di-
rect addressing of up to 16 I/O modules. A dual register
addressing scheme has been adopted to enable direct ad-
dressing of the
”
primary register
”
. To address the
”
auxiliary register
”
, the access must be switched with an
”
auxiliary switching module
”
. Thus a single IN (or OUT)
to the module address will read (or write) into the module
Module ASW
primary register. Accessing the auxiliary register is per-
formed with the same instruction preceded by writing the
module address into the auxiliary switching module. Byte
wide registers are accessed by multiple IN- (or OUT-)
instructions. For more complex peripheral modules, with
a larger number of registers, extended addressing is used.
In this case a bank of up to 16 subport registers are indi-
rectly addressed with the subport address. The first
OUT-instruction writes the subport address to the sub-
address register, the second IN- or OUT-instruction reads
data from or writes data to the addressed subport.
Subaddress Reg.
Subport 0
Subport 1
Subport Fh
Subport Eh
I/O bus
Aux. Reg.
Primary Reg.
Bank of
Primary Regs.
Primary Reg.
Primary Reg.
(Address Pointer)
Auxiliary Switch
Module
Indirect Subport
Access
Dual Register
Access
Single Register
Access
to other modules
Address(M2) Address(ASW) OUT
Aux._Data Address(M2) OUT
Prim._Data Address(M2) OUT
(Primary Register Write)
Prim._Data Address(M3) OUT
(Primary Register Write)
Addr.(SPort) Addr.(M1) OUT
SPort_Data Addr.(M1) OUT
1
2
(Subport Register Write)
3
4
5
1
2
3
6
6
4
5
Example of
qFORTH
Program
Code
Addr.(Mx) = Module Mx Address
Addr.(SPort) = Subport Address
Aux._Data = data to be written into Auxiliary Register
Aux._Data (lo)= data to be written into Auxiliary Register (low nibble)
Prim._Data = data to be written into Primary Register.
Addr.(SPort) Addr.(M1) OUT
1
2
(Subport Register Read)
(Subport Register Write Byte)
Addr.(M1) IN
Address(M2) Address(ASW) OUT
Address(M2) IN
(Auxiliary Register Read)
4
5
Address(M2) IN
(Primary Register Read)
3
Address(M3) IN
(Primary Register Read)
6
Addr.(ASW) = Auxiliary Switch Module Address
Addr.(SPort) Addr.(M1) OUT
SPort_Data(lo) Addr.(M1) OUT
SPort_Data(hi) Addr.(M1) OUT
1
2
2
Addr.(SPort) Addr.(M1) OUT
Addr.(M1) IN
Addr.(M1) IN
1
2
2
(Subport Register Read Byte)
SPort_Data(lo) = data to be written into SubPort (low nibble)
SPort_Data(hi) = data to be written into Subport (high nibble)
(lo) = SPort_Data (low nibble)
(hi) = SPort_Data (high nibble)
Address(M2) Address(ASW) OUT
Aux._Data(lo) Address(M2) OUT
Aux._Data(hi) Address(M2) OUT
(Auxiliary Register Write Byte)
4
5
5
Aux._Data (hi) = data to be written into Auxiliary Register(high nibble)
( Auxiliary Register Write )
13357
(hi)
(lo)
Module M1
Module M2
Module M3
Figure 21. Example of I/O addressing
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