參數(shù)資料
型號(hào)： M44C090
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Low-Current Microcontroller for Wireless Communication
中文描述： 4-BIT, MROM, MICROCONTROLLER, PDSO20
封裝： SSOP-20
文件頁(yè)數(shù)： 34/63頁(yè)
文件大?。?/td> 503K
代理商： M44C090
M44C890
M44C090
Rev.A4, 14-Dec-01
34 (63)
Timer 2 output mode 7: PWM mode:
Pulse
–
width modulation output on Timer 2 output pin (T2O)
In this mode the timer overflow defines the period and the compare register defines the duty cycle. During one period
only the first compare match occurence is used to toggle the timer output flip-flop, until the overflow all further
compare match are ignored. This avoids the stuation that changing the compare register causes the occurence of several
compare match during one period. The resolution at the pulse-width modulation Timer 2 mode 1 is 12-bit and all other
Timer 2 modes are 8-bit.
0
0
50
255
100
0
255 0
150
255 0 50
255 0
100
T2R
Input clock
Counter 2/2
Counter 2/2
OVF2
CM2
INT4
T2O
load the next
T2CO2=150
load
load
T1
T2
T3
T1
T2
T
T
T
T
T
13788
Figure 41. PWM modulation
Timer 2 Registers
Timer 2 has 6 control registers to configure the timer mode, the time interval, the input clock and its output function.
All registers are indirectly addressed using extended addressing as described in section
”
Addressing peripherals
”
. The
alternate functions of the Ports BP41 or BP42 must be selected with the Port 4 control register P4CR, if one of the
Timer 2 modes require an input at T2I/BP41 or an output at T2O/BP42.
Timer 2 Control Register (T2C)
Address:
’
7
’
hex
–
Subaddress:
’
0
’
hex
Bit 3
Bit 2
Bit 1
Bit 0
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T2CS1
T2CS0
Input Clock (CL 2/1) of
Counter Stage 2/1
System clock (SYSCL)
Output signal of Timer 1 (T1OUT)
Internal shift clock of SSI (SCL)
Reserved
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1
1
T2TS = 0, the output flip-flop of Timer 2 is not toggled with the timer start
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