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參數(shù)資料
| 型號(hào)： | M44C090 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Low-Current Microcontroller for Wireless Communication |
| 中文描述： | 4-BIT, MROM, MICROCONTROLLER, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數(shù)： | 28/63頁 |
| 文件大?。?/td> | 503K |
| 代理商： | M44C090 |
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M44C890
M44C090
Rev.A4, 14-Dec-01
28 (63)
Watchdog Control Register (WDC)
Address:
’
7
’
hex
–
Subaddress:
’
A
’
hex
Bit 3 *
WDL
Bit 2
WDR
Bit 1
WDT1
Bit 0
WDT0
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WDC
–
> LSB
Reset value: 1111b
WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no effect. After the
WDL-bit is cleared, the watchdog is active until a system reset or power-on reset occurs.
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WDT1
WDT0 Divider
Delay Time to Reset with
SUBCL = 32 kHz
Delay Time to Reset with
SYSCL = 2 / 1 MHz
0
0
1
1
0
1
0
1
512
2048
16384
131072
15.625 ms
62.5 ms
0.5 s
4 s
0.256 ms / 0.512 ms
1.024 ms / 2.048 ms
8.2 ms / 16.4 ms
65.5 ms / 131 ms
3.3.2
Timer 2
Features: 8/12 bit timer for
Interrupt, square-wave, pulse and duty-cycle
generation
Baud-rate generation for the internal shift register
Manchester and Biphase modulation together with the
SSI
Carrier frequency generation and modulation
together with the SSI
Timer 2 can be used as interval timer for interrupt
generation, as signal generator or as baud-rate generator
and modulator for the serial interface. It consists of a 4-bit
and an 8-bit up counter stage which both have compare
registers. The 4-bit counter stages of Timer 2 are
cascadable as 12-bit timer or as 8-bit timer with 4-bit
prescaler. The timer can also be configured as 8-bit timer
and separate 4-bit prescaler.
The Timer 2 input can be supplied via the system clock,
the external input clock (T2I), the Timer 1 output clock
or the shift clock of the serial interface. The external input
clock T2I is not synchronized with SYSCL. Therefore it
is possible to use Timer 2 with a higher clock speed than
SYSCL. Furthermore with that input clock the Timer 2
operates in the power-down mode SLEEP (CPU core
–
>
sleep and OSC
–
Stop
–
> yes) as well as in the POWER-
DOWN (CPU core
–
> sleep and OSC
–
Stop
–
> no). All
other clock sources supplied no clock signal in SLEEP.
The 4-bit counter stages of Timer 2 have an additional
clock output (POUT).
Its output has a modulator stage that allows the generation
of pulses as well as the generation and modulation of
carrier frequencies. The Timer 2 output can modulate
with the shift register internal data output to generate
Biphase- or Manchester-code.
If the serial interface is used to modulate a bitstream, the
4-bit stage of Timer 2 has a special task. The shift register
can only handle bitstream lengths divisible by 8. For other
lengths, the 4-bit counter stage can be used to stop the
modulator after the right bitcount is shifted out.
If the timer is used for carrier frequency modulation, the
4-bit stage works together with an additional 2-bit duty-
cycle generator like a 6-bit prescaler to generate carrier
frequency and duty cycle. The 8-bit counter is used to en-
able and disable the modulator output for a programmable
count of pulses.
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