參數(shù)資料
型號(hào)： M38K07M4L-XXXHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP64
封裝： 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 92/133頁
文件大?。?/td> 1359K
代理商： M38K07M4L-XXXHP
38K0 Group
Rev.3.00
Oct 05, 2006
page 61 of 129
REJ03B0192-0300
b7
b0
–
RXBUF/
TXBUF
–
0
Index =0116 : Transmit/Receive buffer register (RXBUF/TXBUF) [address 003416]
Bit name
Bit symbol
At reset
Function
H/W
S/W
OO
The data received from an external bus is written here
at the rise timing of external write signal.
The data transmitted to an external bus is written here
at the timing of internal CPU write or memory write.
The receive buffer register (RXBUF) contents can be read out by reading to this address with the CPU. The data which the
CPU has written to this address is stored in the transmit buffer register (TXBUF).
However, do not perform write operation with the CPU to this address if the memory channel direction control bits of
memory channel operation mode register is “102” (transmit mode) and the memory channel status bits of EXB interrupt
source register are “012” or “102” (memory channel being operating).
W
R
Fig. 86 Index01[low]; Structure of Transmit/Receive buffer register
b7
b0
MC_DIR
[1:0]
BURST
b7:b3
–
0
–
Index =0216 : Memory channel operation mode register (MCHMOD) [address 003416]
00000
Bit name
Bit symbol
At reset
Function
H/W
S/W
b1b0
0 0 : Operation disabled
0 1 : Receive mode
1 0 : Transmit mode
1 1 : Do not set.
0 : Cycle mode (each byte transfer according to
assertion or negation)
1 : Burst mode (continuous transfer till the terminal
count)
Write “0” when writing.
“0” is read when reading.
O
–: State remaining
Memory channel direction
control bit
Burst bit
Not used
W
R
Fig. 87 Index02[low]; Structure of Memory channel operation mode register
b7
b0
IM_A
[7:0]
–
0
Index = 0316 : Memory address counter (MEMADL) [address 003416]
Bit name
Bit symbol
At reset
Function
H/W
S/W
OO
–
Register to set the low-order address of memory
channel operation beginning.
This contents are increased each time one memory
access ends.
W
R
Fig. 88 Index03[low]; Structure of Memory address counter
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