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參數(shù)資料
| 型號(hào)： | M38K07M4L-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 86/133頁 |
| 文件大?。?/td> | 1359K |
| 代理商： | M38K07M4L-XXXHP |
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38K0 Group
Rev.3.00
Oct 05, 2006
page 56 of 129
REJ03B0192-0300
qP33/ExINT pin
Any one of the following signals for this pin can be selected:
TxB_RDY (transmit buffer ready) output
RxB_RDY (receive buffer ready) output
Mch_req (memory channel request) output
Either TxB_RDY or RxB_RDY is normally selected. The memory
channel request is for an access request signal to the memory
channel.
In a small system, a data transfer processing to the internal
memory is performed in the interrupt routine. According to that
situation, the 38K0 group has the function automatically to switch
an interrupt factor attached on the interrupt pin by program.
qP40/ExDREQ/RxD pin
This pin is a port at the initial state. Which signal can be set by
program.
RxB_RDY (receive buffer ready) output
Mch_req (memory channel request) output
Mch_req of DMAC is normally selected. The output method of the
memory channel request signal depends on the burst bit (BURST)
of memory channel operation mode register. When the burst bit is
“0”, this signal is periodically output at each 1-byte transfer. (See
Figures 94 and 97.)
When the burst bit is “1”, this signal is continuously output while
the memory address counter is counting from the beginning ad-
dress to the end address (See Figures 95 and 98.)
qP41/ExDACK/TxD pin
This pin is a port at the initial state. The DMA acknowledge signal
can be set by program.
The DMA acknowledge signal DACK = “L” is the same state as
that of CS = “L” and A0 = “L”. Access to multichannel RAM is
started by a rise of read signal or write signal which is set during
this term.
Note: If the DMA acknowledge signal and the chip select signal
are simultaneously active (DACK = “L” and CS = “L”), also
set the address signal A0 to “L”. If A0 is “H”, the memory
channel and the CPU channel are activated simultaneously
and it might cause some error.
qP42/ExTC/SCLK pin
This pin is a port at the initial state. The terminal count signal can
be set by program.
If the terminal count signal is set at one bus cycle while a memory
channel operation write is being performed, the 38K0 group con-
firms that its bus cycle is the write cycle of the last data and sets
the memory channel status bits to “112”, and the interrupt is gener-
ated and the memory channel operation ends even if the memory
address counter has not reached the end address.
The CPU can obtain the last address where the data is written by
reading out the value of memory address counter. (See Figure
96.)
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