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參數(shù)資料
| 型號： | M38K07M4L-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | 10 X 10 MM, 0.50 MM PITCH, PLASTIC, LQFP-64 |
| 文件頁數(shù)： | 100/133頁 |
| 文件大小： | 1359K |
| 代理商： | M38K07M4L-XXXHP |
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38K0 Group
Rev.3.00
Oct 05, 2006
page 69 of 129
REJ03B0192-0300
#0
#1
#2
Mch_req
#0
#1
#2
012
3
4
5
req
010016
010116
010216
010316
ack
DMA acknowledge
ExDACK
mRD
detection
mRD
detection
DMA request
ExDREQ
’
Address ExA0
Chip select ExCS
Read ExRD
Write ExWR
Data DQ0 to DQ7
Internal clock
φ
Transmit buffer TXBUF
Operation enabled
Transmission completed
Main sequencer
Internal memory access
Acknowledgment of
internal memory access
Memory address
Counter end
Burst end
Memory channel operation
end interrupt
<Initial setting>
External I/O configuration register
Set as necessary.
Memory channel operation mode register
MC_DIR[1:0] (Memory channel direction control) = 102 (Transmit mode)
Burst (burst) = “1” (Burst mode)
Memory address counter
(Example) 010016
End address register
(Example) 010216
<Operation start command>
EXB interrupt source enable register
MC_ENB (Memory channel operation enable) = “1” (Operation start)
In the memory channel transmit mode when the command for enabling operation is written, an internal memory access sequence which synchronized with
a rise of
φ is activated.
A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased and assertion of the memory channel request is made.
When a rise of ExRD is detected, an internal memory access sequence which synchronized with a rise of φ is activated.
A data is read out from the internal memory within two clocks at a minimum and this data is stored in the transmit buffer (TXBUF). The memory address
counter is simultaneously increased.
When the read operation from the end address has been completed, the detection circuit of external read signal (ExRD) operation is enabled and negation
of the memory channel request which synchronized with the following
φ is made.
When a rise of ExRD is detected, the memory channel operation sequence ends and the memory channel operation end interrupt is generated.
Dack =
“0”
A0 = “x”
CS = “1”
Dack =
“0”
A0 = “x”
CS = “1”
Dack =
“0”
A0 = “x”
CS = “1”
Fig. 98 Memory channel tranmitting operation (2)
(7) Memory Channel Transmitting Operation
(2)-Burst Mode
Memory channel transmitting operation (2) is shown bellow.
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