Rev.2.00
Nov 23, 2005
page 15 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
I/O PORTS
Direction Registers (Ports P0–P6, P72–P74)
The I/O ports P0–P6, P72–P74 have direction registers which deter-
mine the input/output direction of each individual pin. Each bit in a
direction register corresponds to one pin, each pin can be set to be
input port or output port.
When “0” is written to the bit of the direction register, the correspond-
ing pin becomes an input pin. As for ports P0–P3, when “1” is written
to the bit of the direction register and the segment output disable
register, the corresponding pin becomes an output pin. As for ports
P4–P6, P72–P74, when “1” is written to the bit of the direction regis-
ter, the corresponding pin becomes an output pin.
If data is read from a pin set to output, the value of the port latch is
read, not the value of the pin itself. However, when RTP1, RTP0,
TXOUT1, TXOUT2, T4OUT, T3OUT and T2OUT/CKOUT output are se-
lected, the output value is read, not the value of the port latch. Pins
set to input are floating. If a pin set to input is written to, only the port
output latch is written to and the pin remains floating.
Ports P70, P71
These are input ports which are shared with the voltage multiplier.
When these are read out at using the voltage multiplier, the contents
are “1”.
Pull-up Control
Each individual bit of ports P0–P3 can be pulled up with a program
by setting direction registers and segment output disable registers 0
to 2 (addresses 0FF416 to 0FF616).
The pin is pulled up by setting “0” to the direction register and “1” to
the segment output disable register.
By setting the PULL registers (addresses 0FF016 to 0FE216), ports
P4–P7 can control pull-up with a program.
However, the contents of PULL register do not affect ports pro-
grammed as the output ports.
Fig. 13 Structure of PULL register and segment output disable register
Fig. 12 Structure of ports P0 to P3
Segment output
disable register
Direction register
“0”
“1”
“0”“1”
Input port
No pull-up
Segment
output
Port output
Input port
Pull-up
Initial state
P60 pull-up
P61 pull-up
P62 pull-up
P63 pull-up
P64 pull-up
P65 pull-up
P66 pull-up
P67 pull-up
PULL register 2
(PULL2 : address 0FF116)
b7
b0
P00 pull-up
P01 pull-up
P02 pull-up
P03 pull-up
P04 pull-up
P05 pull-up
P06 pull-up
P07 pull-up
Segment output disable register 0
(SEG0 : address 0FF416)
b7
b0
Note: The PULL register and segment output disable register affect only ports
programmed as the input ports.
0: No pull-up
1: Pull-up
P20 pull-up
P21 pull-up
P22 pull-up
P23 pull-up
P24 pull-up
P25 pull-up
P26 pull-up
P27 pull-up
b7
b0
Segment output disable register 1
(SEG1 : address 0FF516)
P10–P13 pull-up
P14–P17 pull-up
P30–P33 pull-up
P34–P37 pull-up
Not used (return “0 ” when read)
(Do not write to “1 ”)
b7
b0
Segment output disable register 2
(SEG2 : address 0FF616)
0: No pull-up
1: Pull-up
P50 pull-up
P51 pull-up
P52 pull-up
P53 pull-up
P54 pull-up
P55 pull-up
P56 pull-up
P57 pull-up
PULL register 1
(PULL1 : address 0FF016)
b7
b0
0: No pull-up
1: Pull-up
P40–P43 pull-up
P44–P47 pull-up
P72–P74 pull-up
Not used (return “0 ” when read)
(Do not write to “1 ”)
PULL register 3
(PULL3 : address 0FF216)
b7
b0
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up
0: No pull-up
1: Pull-up