參數(shù)資料
型號： M38C59GFHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 6.25 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù)： 39/71頁
文件大小： 939K
代理商： M38C59GFHP
Rev.2.00
Nov 23, 2005
page 44 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
LCD DRIVE CONTROL CIRCUIT
The 38C5 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
LCD display RAM
Segment output disable register
LCD mode register
Selector
Timing controller
Common driver
Segment driver
Bias control circuit
A maximum of 36 segment output pins and 8 common output pins
can be used.
Up to 256 pixels can be controlled for an LCD display. When the LCD
enable bit is set to “1” after data is set in the LCD mode register, the
segment output disable register, and the LCD display RAM, the LCD
drive control circuit starts reading the display data automatically, per-
forms the bias control and the duty ratio control, and displays the
data on the LCD panel.
Fig. 40 Structure of LCD related registers
Table 9 Maximum number of display pixels at each duty ratio
Duty ratio
Maximum number of display pixels
36 dots
or 8 segment LCD 4 digits
72 dots
or 8 segment LCD 9 digits
108 dots
or 8 segment LCD 12 digits
144 dots
or 8 segment LCD 18 digits
256 dots
or 8 segment LCD 32 digits
1
2
3
4
8
Segment output disable bit 0
0 : Segment output SEG8
1 : Output port P00
Segment output disable bit 1
0 : Segment output SEG9
1 : Output port P01
Segment output disable bit 2
0 : Segment output SEG10
1 : Output port P02
Segment output disable bit 3
0 : Segment output SEG11
1 : Output port P03
Segment output disable bit 4
0 : Segment output SEG12
1 : Output port P04
Segment output disable bit 5
0 : Segment output SEG13
1 : Output port P05
Segment output disable bit 6
0 : Segment output SEG14
1 : Output port P06
Segment output disable bit 7
0 : Segment output SEG15
1 : Output port P07
Segment output disable register 0
(SEG0 : address 0FF416)
b7
b0
LCD mode register 1
(LM1 : address 001316)
Duty ratio selection bits
b2 b1 b0
0 0 0 : 1 (Static)
0 0 1 : 2 (use COM0,COM1)
0 1 0 : 3 (use COM0–COM2)
0 1 1 : 4 (use COM0–COM3)
1 0 0 to 1 1 0: Not available
1 1 1 : 8 (COM0–COM7)
Bias control bit
0 : 1/3 bias (Note 1)
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
LCD circuit divider division ratio selection bits
b6 b5
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note 2)
0 : f(XCIN)/32
1 :
φSOURCE/8192
Note : LCDCK is a clock for an LCD timing controller.
b7
b0
Segment output disable bit 8
0 : Segment output SEG0
1 : Output port P20
Segment output disable bit 9
0 : Segment output SEG1
1 : Output port P21
Segment output disable bit 10
0 : Segment output SEG2
1 : Output port P22
Segment output disable bit 11
0 : Segment output SEG3
1 : Output port P23
Segment output disable bit 12
0 : Segment output SEG4
1 : Output port P24
Segment output disable bit 13
0 : Segment output SEG5
1 : Output port P25
Segment output disable bit 14
0 : Segment output SEG6
1 : Output port P26
Segment output disable bit 15
0 : Segment output SEG7
1 : Output port P27
Segment output disable register 1
(SEG1 : address 0FF516)
b7
b0
Segment output disable bit 16
0 : Segment output SEG16–SEG19
1 : Output port P10–P13
Segment output disable bit 17
0 : Segment output SEG20–SEG23
1 : Output port P14–P17
Segment output disable bit 18
0 : Segment output SEG24–SEG27
1 : Output port P30–P33
Segment output disable bit 19
0 : Segment output SEG28–SEG31
1 : Output port P34–P37
Do not write “1” to these bits.
Segment output disable register 2
(SEG2 : address 0FF616)
b7
b0
Notes 1: When “1” is selected as duty ratio by the duty ratio selection bits, set “1” to the bias
control bit.
2: LCDCK is the clock for the LCD timing controller.
φ SOURCE represents the supply
source of internal clock
φ. XIN input: in the middle- or high-speed mode, Internal on-
chip oscillator divided by 4 in the on-chip oscillator mode, and Sub clock in the low-
speed mode.
3: Only pins set to output ports by the direction register can be controlled to switch to
output ports or segment outputs by the segment output disable register.
4: When disabling the voltage multiplier circuit, the C1 and C2 pins function as input
ports P70/INT01, P71/INT11.
b7
b0
LCD mode register 2
(LM2 : address 001416)
Voltage multiplier circuit control bit
0 : Voltage multiplier circuit disabled
(Input ports P70/INT01, P71/INT11)
1 : Voltage multiplier circuit enabled
VL3 connection bit
0 : Connect VL3 to VCC.
1 : Leave VL3 and VCC open.
Not available
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