參數(shù)資料
型號: M38C59GFHP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, OTPROM, 6.25 MHz, MICROCONTROLLER, PQFP80
封裝: 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù): 46/71頁
文件大?。?/td> 939K
代理商: M38C59GFHP
Rev.2.00
Nov 23, 2005
page 50 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because
of a software run-away). The watchdog timer consists of an 8-bit
counter.
Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register, each watch-
dog timer is set to “FF16.” Instructions such as STA, LDM and CLB to
generate the write signals can be used.
The written data in bits 0 to 5 are not valid, and the above values are
set.
Standard Operation of Watchdog Timer
The watchdog timer is in the stop state at reset and the watchdog
timer starts to count down by writing an optional value in the watch-
dog timer control register. An internal reset occurs at an underflow of
the watchdog timer. Then, reset is released after the reset release
time is elapsed, the program starts from the reset vector address.
Normally, writing to the watchdog timer control register before an
underflow of the watchdog timer is programmed. If writing to the watch-
dog timer control register is not executed, the watchdog timer does
not operate.
When reading the watchdog timer control register is executed, the
contents of the high-order 6-bit counter and the STP instruction dis-
able bit (bit 6), and the count source selection bit (bit 7) are read out.
Bit 6 of Watchdog Timer Control Register
When bit 6 of the watchdog timer control register is “0”, the MCU
enters the stop mode by execution of STP instruction.
Just after releasing the stop mode, the watchdog timer restarts
counting(Note). When executing the WIT instruction, the watchdog
timer does not stop.
When bit 6 is “1”, execution of STP instruction causes an internal
reset. When this bit is set to “1” once, it cannot be rewritten to “0” by
program. Bit 6 is “0” at reset.
The time until the underflow of the watchdog timer register after writ-
ing to the watchdog timer control register is executed is as follows
(when the bit 7 of the watchdog timer control register is “0”) ;
at high-speed and middle-speed mode (f(XIN)) = 8 MHz): 32.768
ms
at low-speed mode (f(XCIN) = 32 KHz): 8.19s
s Note
The watchdog timer continues to count even during the wait time set
by timer 1 and timer 2 to release the stop state and in the wait mode.
Accordingly, do not underflow the watchdog timer in this time.
Fig. 46 Block diagram of Watchdog timer
Fig. 47 Structure of Watchdog timer control register
1/1024
RESET
1/4
φ SOURCE
Undefined instruction
Reset
Wait until reset release
Data bus
Watchdog timer
count source
selection bit
Reset
circuit
STP instruction disable bit
Watchdog timer
H (6)
Internal reset
STP instruction
Watchdog timer
L (2)
“FF16” is set when
watchdog timer
control register is
written to.
“0”
“1”
b0
STP instruction disable bit
0: Entering stop mode by execution of STP instruction
1: Internal reset by execution of STP instruction
Watchdog timer count source selection bit
0:
φSOURCE/1024
1:
φSOURCE/4
Watchdog timer H (for read-out of high-order 6 bit)
“FF16” is set to watchdog timer by writing to these bits.
Watchdog timer control register
(WDTCON : address 002916)
b7
Note:
φ SOURCE represents the supply source of internal clock φ.
XIN input: in the middle- or high-speed mode, Internal on-chip oscillator divided by 4 in the on-chip oscillator mode,
and Sub clock in the low-speed mode.
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