參數(shù)資料
型號(hào)： M38C59GFHP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 6.25 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁(yè)數(shù)： 59/71頁(yè)
文件大?。?/td> 939K
代理商： M38C59GFHP
Rev.2.00
Nov 23, 2005
page 62 of 75
REJ03B0098-0200
38C5 Group (One Time PROM version)
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After a
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the index X mode (T) and the decimal mode
(D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immediately
after they have been written. After writing to an interrupt request reg-
ister, execute at least one instruction before performing a BBC or
BBS instruction.
Decimal Calculations
To calculate in decimal notation, set the decimal mode flag (D) to
“1,” then execute an ADC or SBC instruction. After executing an
ADC or SBC instruction, execute at least one instruction before
executing an SEC, CLC, or CLD instruction.
In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
Timers
If a value n (between 0 and 255) is written to a timer latch, the
frequency division ratio is 1/(n+1).
The timers share the one frequency divider to generate the count
source. Accordingly, when each timer starts operating, initializing
the frequency divider is not executed. Therefore, when the frequency
divider is selected for the count source, the delay of the maximum
one cycle of the count source is generated until the timer starts
counting or the waveform is output from timer starts operating. Also,
the count source cannot be checked externally.
Multiplication and Division Instructions
The index X mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read. The fol-
lowing cannot be used:
The data transfer instruction (LDA, etc.)
The operation instruction when the index X mode flag (T) is “1”
The addressing mode which uses the value of a direction register
as an index
The bit-test instruction (BBC or BBS, etc.) to a direction register
The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direction
registers.
Serial Interface
In clock synchronous serial I/O, if the receive side is using an exter-
nal clock and it is to output the SRDY signal, set the transmit enable
bit, the receive enable bit, and the SRDY output enable bit to “1.”
Serial I/O continues to output the final bit from the TXD pin after trans-
mission is completed.
A/D Converter
The comparator is constructed linked to a capacitor. The conversion
accuracy may be low because the change is lost if the conversion
speed is not enough.
Accordingly, set f(XIN) to at least 500 kHz during A/D conversion in
the middle- or high- speed mode.
Also, do not execute the STP and WIT instructions during the A/D
conversion.
In the low-speed mode, since the A/D conversion is executed by the
built-in self-oscillation circuit, the minimum value of f(XIN) frequency.
Instruction Execution Time
The instruction execution time is obtained by multiplying the number
of cycles shown in the list of machine instructions by the period of the
internal clock
φ.
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