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參數資料
| 型號： | M38B79MFH-A157FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數： | 89/109頁 |
| 文件大?。?/td> | 1559K |
| 代理商： | M38B79MFH-A157FP |
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89
38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
Functional Outline (serial I/O mode)
In the serial I/O mode, data is transferred synchronously with the
clock using serial input/output. The input data is read from the
SDA pin into the internal circuit synchronously with the rising edge
of the serial clock pulse; the output data is output from the SDA
pin synchronously with the falling edge of the serial clock pulse.
Data is transferred in units of eight bits.
In the first transfer, the user inputs the command code. This is fol-
lowed by address input and data input/output according to the
contents of the command. Table 20 shows the software com-
mands used in the serial I/O mode. The following explains each
software command.
Table 20 Software command (serial I/O mode)
Read
Program
Program verify
Erase
Erase verify
Error check
Number of transfers
Command
First command
code input
00
16
40
16
C0
16
20
16
A0
16
80
16
Read address L (Input)
Program address L (Input)
Verify data (Output)
20
16
(Input)
Verify address L (Input)
Error code (Output)
Second
Read address H (Input)
Program address H (Input)
—————
—————
Verify address H (Input)
—————
Third
Fourth
Read data (Output)
Program data (Input)
—————
—————
Verify data (Output)
—————
G
Read command
Input command code 00
16
in the first transfer. Proceed and input
the low-order 8 bits and the high-order 8 bits of the address and
pull the OE pin low. When this is done, the M38B79FF reads out
the contents of the specified address, and then latchs it into the in-
ternal data latch. When the OE pin is released back high and se-
rial clock is input to the SCLK pin, the read data that has been
latched into the data latch is serially output from the SDA pin.
Fig. 92 Timings during reading
“
L
”
SCLK
BUSY
OE
SDA
t
CH
A
0
A
7
A
8
A
15
D
0
D
7
t
CH
t
CR
Command code input (00
16
)
Read address input (L)
Read address input (H)
Read data output
t
WR
Read
t
RC
Note :
When outputting the read data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th
(C-E)
after the last rising edge of SCLK (at the 8th bit).
0 0 0 0 0 0 0 0
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