38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
30
(1) Serial I/O1 operation
Either the internal synchronous clock or external synchronous
clock can be selected by the serial I/O1 synchronous clock selec-
tion bits (b2 and b3 of address 0019
16
) of serial I/O1 control
register 1 as synchronous clock for serial transfer.
The internal synchronous clock has a built-in dedicated divider
where 7 different clocks are selected by the internal synchronous
clock selection bits (b5, b6 and b7 of address 001C
16
) of serial
I/O1 control register 3.
The PB
1
/S
RDY1
, PB
2
/S
BUSY1
, and PB
3
/S
STB1
pins each select ei-
ther I/O port or handshake I/O signal by the serial I/O1
synchronous clock selection bits (b2 and b3 of address 0019
16
) of
serial I/O1 control register 1 as well as the PB
1
/S
RDY1
PB
2
/
S
BUSY1
pin control bits (b0 to b3 of address 001A
16
) of serial
I/O1 control register 2.
For the SOUT
1
being used as an output pin, either CMOS output
or N-channel open-drain output is selected by the PB
5
/S
OUT1
P-
channel output disable bit (b7 of address 001A
16
) of serial I/O1
control register 2.
Either output active or high-impedance can be selected as a
S
OUT1
pin state at serial non-transfer by the S
OUT1
pin control bit
(b6 of address 001A
16
) of serial I/O1 control register 2. However,
when the external synchronous clock is selected, perform the fol-
lowing setup to put the S
OUT1
pin into a high-impedance state:
When the S
CLK1
input is
“
H
”
after completion of transfer, set the
S
OUT1
pin control bit to
“
1
”
.
When the S
CLK1
input goes to
“
L
”
after the start of the next serial
transfer, the S
OUT1
pin control bit is automatically reset to
“
0
”
and
put into an output active state.
Regardless of whether the internal synchronous clock or external
synchronous clock is selected, the full duplex mode and the trans-
mit-only mode are available for serial transfer, one of which is
selected by the transfer mode selection bit (b5 of address 0019
16
)
of serial I/O1 control register 1.
Either LSB first or MSB first is selected for the I/O sequence of the
serial transfer bit strings by the transfer direction selection bit (b6
of address 0019
16
) of serial I/O1 control register 1.
When using serial I/O1, first select either 8-bit serial I/O or auto-
matic transfer serial I/O by the serial transfer selection bits (b0 and
b1 of address 0019
16
) of serial I/O1 control register 1, after
completion of the above bit setup. Next, set the serial I/O initializa-
tion bit (b4 of address 0019
16
) of serial I/O1 control register 1 to
“
1
”
(Serial I/O enable) .
When stopping serial transfer while data is being transferred, re-
gardless of whether the internal or external synchronous clock is
selected, reset the serial I/O initialization bit (b4) to
“
0
”
.
Fig. 23 Structure of serial I/O1 control register 3
7 b
6
b
5
4 b
3
b
2
1 b
0
S
(
S
u
b
4
0
0
e
r
O
i
a
1
l
C
I
/
O
O
1
N
3
c
o
(
n
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t
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r
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1
l
3
r
e
)
:
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a
i
s
d
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r
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3
s
I
r
s
0
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1
C
1
6
)
A
t
3
0
0
o
b
m
2
b
0
0
a
1
0
0
:
1
1
t
0
0
1
i
c
t
r
a
n
s
f
e
r
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a
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:
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k
k
s
s
1
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0
1
:
:
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3
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3
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.
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b
0
0
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n
t
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b
0
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0
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r
b
n
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0
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a
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s
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i
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7
6
:
:
:
:
:
:
:
f
f
f
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(
(
(
(
(
(
(
X
I
X
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X
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X
I
X
I
X
I
X
I
N
)
N
)
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)
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)
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)
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)
N
)
/
/
/
/
/
/
/
4
8
1
3
6
1
2
6
2
4
2
5
o
o
8
6
r
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(
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f
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r
f
(
I
I
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)
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)
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/
8
1
/
/
/
N
)
I
6
3
6
1
/
/
N
)
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)
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)
I
2
4
2
2
5
8
5
1
6
2
N
)