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參數(shù)資料
| 型號： | M38B79MFH-A157FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 26/109頁 |
| 文件大?。?/td> | 1559K |
| 代理商： | M38B79MFH-A157FP |
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
26
16-Bit Timer
Timer X is a 16-bit timer that can be selected in one of four modes by
the Timer X mode registers 1, 2 and can be controlled for the timer X
write and the real time port by setting the timer X mode registers.
Read and write operation on 16-bit timer must be performed for both
high- and low-order bytes. When reading a 16-bit timer, read from
the high-order byte first. When writing to 16-bit timer, write to the low-
order byte first. The 16-bit timer cannot perform the correct operation
when reading during write operation, or when writing during read
operation.
G
Timer X
Timer X is a down-counter. When the timer reaches
“
0000
16
”
, an
underflow occurs with the next count pulse. Then the contents of the
timer latch is reloaded into the timer and the timer continues down-
counting. When a timer underflows, the interrupt request bit corre-
sponding to that timer is set to
“
1
”
.
(1) Timer mode
A count source can be selected by setting the Timer X count source
selection bits (bits 1 and 2) of the Timer X mode register 1.
(2) Pulse output mode
Each time the timer underflows, a signal output from the CNTR
2
pin
is inverted. Except for this, the operation in pulse output mode is the
same as in timer mode. When using a timer in this mode, set the port
shared with the CNTR
2
pin to output.
(3) Event counter mode
The timer counts signals input through the CNTR
2
pin. Except for
this, the operation in event counter mode is the same as in timer
mode. When using a timer in this mode, set the port shared with the
CNTR
2
pin to input.
(4) Pulse width measurement mode
A count source can be selected by setting the Timer X count source
selection bits (bits 1 and 2) of the Timer X mode register 1. When
CNTR
2
active edge switch bit is
“
0
”
, the timer counts while the input
signal of the CNTR
2
pin is at
“
H
”
. When it is
“
1
”
, the timer counts
while the input signal of the CNTR
2
pin is at
“
L
”
. When using a timer
in this mode, set the port shared with the CNTR
2
pin to input.
I
Note
Timer X Write Control
If the timer X write control bit is
“
0
”
, when the value is written in the
address of timer X, the value is loaded in the timer X and the latch at
the same time.
If the timer X write control bit is
“
1
”
, when the value is written in the
address of timer X, the value is loaded only in the latch. The value in
the latch is loaded in timer X after timer X underflows.
When the value is written in latch only, unexpected value may be set
in the high-order counter if the writing in high-order latch and the
underflow of timer X are performed at the same timing.
Real Time Port Control
While the real time port function is valid, data for the real time port
are output from ports P9
4
and P9
5
each time the timer X underflows.
(However, if the real time port control bit is changed from
“
0
”
to
“
1
”
,
data are output independent of the timer X.) When the data for the
real time port is changed while the real time port function is valid, the
changed data are output at the next underflow of timer X.
Before using this function, set the corresponding port direction regis-
ters to output mode.
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