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| 型號(hào)： | M38B79MFH-A157FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 60/109頁 |
| 文件大?。?/td> | 1559K |
| 代理商： | M38B79MFH-A157FP |
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38B7 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
PRELIMINARY
Notice: This is not a final specification.
change.
Some parametric limits are subject to
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A-D control circuit
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(
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(Address 0034
16
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A-D conversion register (L)
A-D CONVERTER
The 38B7 group has a 10-bit A-D converter. The A-D converter
performs successive approximation conversion.
[A-D Conversion Register] ADH, ADL
One of these registers is a high-order register, and the other is a
low-order register. The high-order 8 bits of a conversion result is
stored in the A-D conversion register (high-order) (address
0034
16
), and the low-order 2 bits of the same result are stored in
bit 7 and bit 6 of the A-D conversion register (low-order) (address
0033
16
).
During A-D conversion, do not read these registers.
[AD/DA Control Register] ADCON
This register controls A-D converter. Bits 3 to 0 are analog input
pin selection bits. Bit 4 is an AD conversion completion bit and
“
0
”
during A-D conversion. This bit is set to
“
1
”
upon completion of A-
D conversion.
A-D conversion is started by writing
“
0
”
in this bit.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between
AVss and V
REF
by 1024, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports PA
7
/AN
7
–
PA
0
/
AN
0
, and P9
7
/B
UZ02
/AN
15
to P9
0
/S
IN3
/AN
8
and inputs it to the
comparator.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog
inputvoltage with the comparison voltage and stores the result in
the A-D conversion register. When an A-D conversion is com-
pleted, the control circuit sets the AD conversion completion bit
and the AD conversion interrupt request bit to
“
1
”
.
Note that the comparator is constructed linked to a capacitor, so
that set f(X
IN
) to at least 250 kHz during A-D conversion. Addition-
ally, bit 7 of the CPU mode register (address 003B
16
) must be set
to
“
0
”
.
Fig. 61 Block diagram of A-D converter
Fig. 60 Structure of AD/DA control register
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