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| 型號： | M38B57M6-126FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SENSOR HALL EFFECT DIFF SPEED |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 47/69頁 |
| 文件大小： | 1011K |
| 代理商： | M38B57M6-126FP |
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MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
47
PRELIMINARY
Notice: This s not a final specification.
Some parametric imits are subject to change.
A-D Converter
The 38B5 group has a 10-bit A-D converter. The A-D converter per-
forms successive approximation conversion.
[A-D Conversion Register] AD
One of these registers is a high-order register, and the other is a low-
order register. The high-order 8 bits of a conversion result is stored
in the A-D conversion register (high-order) (address 0034
16
), and
the low-order 2 bits of the same result are stored in bit 7 and bit 6 of
the A-D conversion register (low-order) (address 0033
16
).
During A-D conversion, do not read these registers.
[A-D Control Register] ADCON
This register controls A-D converter. Bits 3 to 0 are analog input pin
selection bits. Bit 4 is an AD conversion completion bit and “0” during
A-D conversion. This bit is set to “1” upon completion of A-D conver-
sion.
A-D conversion is started by setting “0” in this bit.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AV
SS
and V
REF
, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports P7
7
/AN
7
–P7
0
/
AN
0
, and P6
5
/S
STB1
/AN
11
–P6
2
/S
RDY1
/AN
8
and inputs it to the com-
parator.
When port P6
4
is selected as an analog input pin, an external inter-
rupt function (INT
4
) is invalid.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input
voltage with the comparison voltage and stores the result in the A-D
conversion register. When an A-D conversion is completed, the
control circuit sets the AD conversion completion bit and the AD
Fig. 52 Block Diagram of A-D Converter
conversion interrupt request bit to “1.”
Note that the comparator is constructed linked to a capacitor, so set
f(X
IN
) to at least 250 kHz during A-D conversion. Use a CPU system
clock dividing the main clock X
IN
as the internal system clock.
Fig. 51 Structure of A-D Control Register
Data bus
AV
SS
V
REF
A-D interrupt request
b7
b0
4
P7
0
/AN
0
P7
1
/AN
1
P7
2
/AN
2
P7
3
/AN
3
P7
4
/AN
4
P7
5
/AN
5
P7
6
/AN
6
P7
7
/AN
7
P6
2
/S
RDY1
/AN
8
P6
3
/AN
9
P6
4
/INT
4
/S
BUSY1
/AN
10
P6
5
/S
STB1
/AN
11
A-D control register
C
Comparator
A-D control circuit
A-D conversion register (H) A-D conversion register (L)
(Address 0034
16
)
(Address 0033
16
)
Resistor ladder
AD conversion result stored bits
A-D conversion register (high-order)
(ADH: address 0034
16
)
b7
b0
Analog input pin selection bits
0000: P7
0
/AN
0
0001: P7
1
/AN
1
0010: P7
2
/AN
2
0011: P7
3
/AN
3
0100: P7
4
/AN
4
0101: P7
5
/AN
5
0110: P7
6
/AN
6
0111: P7
7
/AN
7
1000: P6
2
/S
RDY1
/AN
8
1001: P6
3
/AN
9
1010: P6
4
/INT
4
/S
BUSY1
/AN
10
1011: P6
5
/S
STB1
/AN
11
A-D control register
(ADCON: address 0032
16
)
AD conversion completion bit
0: Conversion in progress
1: Conversion completed
Not used (returns “0” when read)
b7
b0
Not used (returns “0” when read)
AD conversion result stored bits
A-D conversion register (low-order)
(ADL: address 0033
16
)
b7
b0
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