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| 型號： | M38B57M6-126FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SENSOR HALL EFFECT DIFF SPEED |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 43/69頁 |
| 文件大小： | 1011K |
| 代理商： | M38B57M6-126FP |
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MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
43
PRELIMINARY
Notice: This s not a final specification.
Some parametric imits are subject to change.
Digit data protect function
The FLD automatic display RAM is provided with a data protect
function that disables the RAM area data to be rewritten as digit
data.
This function can disable data from being written in optional bits in
the RAM area corresponding to P1 to P3. A programming load can
be reduced by protecting an area that requires no change after
data such as digit data is written.
Write digit data beforehand; then set “1” in the corresponding bits.
With this, the setting is completed.
The data protect area becomes the maximum RAM area of P1 and
P3. For example, when bit 0 of P1 is protected in the 16-
timingordinary mode, bits 0 of RAM addresses 0FD0
16
to 0FDF
16
can be protected. Likewise, in the 16-timinggradation display mode,
bits 0 of addresses 0FD0
16
to 0FDF
16
and 0F80
16
to 0F8F
16
can be
protected. In the 32-timing mode, bits 0 of addresses 0FA0
16
to
0FBF
16
can be protected.
Fig. 46 Structure of FLDRAM Write Disable Register
b7
b0
P1FLDRAM write disable register
(P1FLDRAM : address 0EF2
16
)
FLDRAM corresponding to P1
0
FLDRAM corresponding to P1
1
FLDRAM corresponding to P1
2
FLDRAM corresponding to P1
3
FLDRAM corresponding to P1
4
FLDRAM corresponding to P1
5
FLDRAM corresponding to P1
6
FLDRAM corresponding to P1
7
b7
b0
0: Operating normally
1: Write disabled
P3FLDRAM write disable register
(P3FLDRAM : address 0EF3
16
)
FLDRAM corresponding to P3
0
FLDRAM corresponding to P3
1
FLDRAM corresponding to P3
2
FLDRAM corresponding to P3
3
FLDRAM corresponding to P3
4
FLDRAM corresponding to P3
5
FLDRAM corresponding to P3
6
FLDRAM corresponding to P3
7
0: Operating normally
1: Write disabled
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