MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
39
PRELIMINARY
Notice: This s not a final specification.
Some parametric imits are subject to change.
FLD automatic display RAM
The FLD automatic display RAM uses the 160 bytes of addresses
0F60
16
to 0FFF
16
. For FLD, the 3 modes of 16-timing ordinary mode,
16-timinggradation display mode and 32-timing mode are available
depending on the number of timings and the presence/absence of
gradation display.
The automatic display RAM in each mode is as follows:
(1) 16-timingOrdinary Mode
The 80 bytes of addresses 0FB0
16
to 0FFF
16
are used as a FLD
display data store area. Because addresses 0F60
16
to 0FAF
16
are not used as the automatic display RAM, they can be the ordi-
nary RAM or serial I/O automatic reverse RAM.
(2) 16-timingGradation Display Mode
The 160 bytes of addresses 0F60
16
to 0FFF
16
are used. The 80
bytes of addresses 0FB0
16
to 0FFF
16
are used as an FLD dis-
play data store area, while the 80 bytes of addresses 0F60
16
to
0FAF
16
are used as a gradation display control data store area.
(3) 32-timing Mode
The 160 bytes of addresses 0F60
16
to 0FFF
16
are used as an
FLD display data store area.
[FLD Data Pointer and FLD Data Pointer Reload Register]
FLDDP (0EF8
16
)
Both the FLD data pointer and FLD data pointer reload register are
8-bit registers assigned at address 0EF8
16
. When writing data to this
address, the data is written to the FLD data pointer reload register;
when reading data from this address, the value in the FLD data pointer
is read.
Fig. 42 FLD Automatic Display RAM Assignment
16-timingordinary mode
0FFF
16
0FB0
16
0F60
16
0FFF
16
0F60
16
0FFF
16
0FB0
16
0F60
16
16-timinggradation display mode
32-timing mode
1 to 32 timing display
data stored area
Gradation display
control data stored
area
1 to 16 timing display
data stored area
1 to 16 timing display
data stored area
Not used