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參數(shù)資料
| 型號(hào)： | M38B57M6-126FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SENSOR HALL EFFECT DIFF SPEED |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 45/69頁 |
| 文件大?。?/td> | 1011K |
| 代理商： | M38B57M6-126FP |
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MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
45
PRELIMINARY
Notice: This s not a final specification.
Some parametric imits are subject to change.
Timing setting
Each timing is set by the FLDC mode register, Tdisp time set regis-
ter, Toff1 time set register, and Toff2 time set register.
Tdisp time setting
Set the Tdisp time by the Tdisp counter count source selection bit of
the FLDC mode register and the Tdisp time set register.
Supposing that the value of the Tdisp time set register is n, the
Tdisp time is represented as Tdisp = (n+1)
t (t: count source
synchronization).
When the Tdisp counter count source selection bit of the FLDC mode
register is “0” and the value of the Tdisp time set register is 200
(C8
16
), the Tdisp time is: Tdisp = (200+1)
4 (at X
IN
= 4 MHz) = 804
μs. When reading the Tdisp time set register, the value in the
counter is read out.
Toff1 time setting
Set the Toff1 time by the Toff1 time set register.
Supposing that the value of the Toff1 time set register is n1, the
Toff1 time is represented as Toff1 = n1
t.
When the Tdisp counter count source selection bit of the FLDC mode
register is “0” and the value of the Toff1 time set register is 30
(1E
16
), Toff1 = 30
4 (at X
IN
= 4 MHz) = 120 μs.
Toff2 time setting
Set the Toff2 time by the Toff2 time set register.
Supposing that the value of the Toff2 time set register is n2, the
Toff2 time is represented as Toff2 = n2
t.
When the Tdisp counter count source selection bit of the FLDC mode
register is “0” and the value of the Toff2 time set register is 180
(B4
16
), Toff2 = 180
4 (at X
IN
= 4 MHz) = 720 μs.
This Toff2 time setting is valid only for FLD ports which are in the
gradation display mode and whose gradation display control RAM
value is “1.”
FLD automatic display start
To perform FLD automatic display, set the following registers.
Port P0FLD/port switch register
Port P2FLD/port switch register
Port P8FLD/port switch register
FLDC mode register
Tdisp time set register
Toff1 time set register
Toff2 time set register
FLD data pointer
FLD automatic display mode is selected by writing “1” to the bit 0 of
the FLDC mode register (address 0EF4
16
), and the automatic dis-
play is started by writing “1” to bit 1. During FLD automatic display,
bit 1 of the FLDC mode register (address 0EF4
16
) always keeps “1,”
and FLD automatic display can be interrupted by writing “0” to bit 1.
Key-scan
When a key-scan is performed with the segment during key-scan
blanking period Tscan, take the following sequence:
1. Write “0” to bit 0 of the FLDC mode register (address 0EF4
16
).
2. Set the port corresponding to the segment for key-scan to the
output port.
3. Perform the key-scan.
4. After the key-scan is performed, write “1” to bit 0 of FLDC mode
register (address 0EF4
16
).
I
Note
When performing a key-scan according to the above steps 1 to 4,
take the following points into consideration.
1. Do not set “0” in bit 1 of the FLDC mode register (address 0EF4
16
).
2. Do not set “1” in the ports corresponding to digits.
P8
4
to P8
7
FLD Output Reverse Function
P8
4
to P8
7
are provided with a function to reverse the polarity of the
FLD output. This function is useful in adjusting the polarity when
using an externally installed driver.
The output polarity can be reversed by setting bit 0 of the port P8
FLD output control register to “1.”
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