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| 型號(hào)： | M38B57M6-126FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SENSOR HALL EFFECT DIFF SPEED |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 46/69頁(yè) |
| 文件大?。?/td> | 1011K |
| 代理商： | M38B57M6-126FP |
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MITSUBISHI MICROCOMPUTERS
38B5 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
46
PRELIMINARY
Notice: This s not a final specification.
Some parametric imits are subject to change.
Fig. 50 Structure of P8FLD Output Control Register
Fig. 49 FLDC Timing
P8FLD output control register
(P8FLDCON: address 0EFC
16
)
P8
4
–P8
7
FLD output reverse bits
0: Output normally
1: Reverse output
Not available (returns “0” when read)
b7
b0
Toff1
Tdisp
Segment
Digit
Segment
Digit output
Segment setting by software
FLD blanking interrupt request occurs
at the falling edge of the last timing.
FLD digit interrupt request occurs at the rising
edge of digit (each timing).
Tdisp
Tscan
Repeat synchronous
Tn
Tn-1 Tn-2
T4
T3
T2
T1
Toff1
Toff2
Tdisp
Segment
Digit
When a gradation display mode is selected
Pin under the condition that bit 5 of the
FLDC mode register is “1,” and the
corresponding gradation display control
data value is “1.”
n: Number of timing
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