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參數(shù)資料
| 型號： | M38503M4H |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 51/86頁 |
| 文件大小： | 1193K |
| 代理商： | M38503M4H |
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51
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Software Commands
Table 14 lists the software commands. By entering a software com-
mand from the data I/O pins (D
0
–
D
7
) in Write mode, specify the con-
tent of the operation, such as erase or program operation, to be per-
formed.
The following explains the content of each software command.
Read Array Command (FF
16
)
The read array mode is entered by writing the command code
“
FF
16
”
in the first bus cycle. When an address to be read is input in one of
the bus cycles that follow, the content of the specified address is
output from the data I/O pins (D
0
–
D
7
).
The read array mode is retained intact until another command is writ-
ten.
The read array mode is also selected automatically when the device
is powered on and after it exits deep power down mode.
Command
Read array
Read status register
Clear status register
Program
All block erase
Block erase
Mode
Write
Write
Write
Write
Write
Write
Address
X
(Note 4)
X
X
X
X
X
Data
(D
0
to D
7
)
FF
16
70
16
50
16
40
16
20
16
20
16
Mode
Read
Write
Write
Write
Address
X
WA
(Note 2)
X
BA
(Note 3)
Data
(D
0
to D
7
)
SRD
(Note 1)
WD
(Note 2)
20
16
D0
16
First bus cycle
Second bus cycle
Notes 1:
SRD = Status Register Data
2:
WA = Write Address, WD = Write Data
3:
BA = Block Address (Enter the maximum address of each block)
4:
X denotes a given address in the user ROM area or boot ROM area.
Read Status Register Command (70
16
)
When the command code
“
70
16
”
is written in the first bus cycle, the
content of the status register is output from the data I/O pins (D
0
–
D
7
)
by a read in the second bus cycle. Since the content of the status
register is updated at the falling edge of OE or CE, the OE or CE
signal must be asserted each time the status is read. The status
register is explained in the next section.
Clear Status Register Command (50
16
)
This command is used to clear the bits SR4,SR5 of the status regis-
ter after they have been set. These bits indicate that operation has
ended in an error. To use this command, write the command code
“
50
16
”
in the first bus cycle.
Table 14 Software command list (parallel I/O mode)
Cycle number
1
2
1
2
2
2
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