參數(shù)資料
型號(hào)： M38503M4H
廠(chǎng)商： Mitsubishi Electric Corporation
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 40/86頁(yè)
文件大?。?/td> 1193K
代理商： M38503M4H
40
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
CPU Rewrite Mode
In CPU rewrite mode, the on-chip flash memory can be operated on
(read, program, or erase) under control of the Central Processing
Unit (CPU).
In CPU rewrite mode, only the user ROM area shown in Figure 44
can be rewritten; the Boot ROM area cannot be rewritten. Make sure
the program and block erase commands are issued for only the user
ROM area and each block area.
The control program for CPU rewrite mode can be stored in either
user ROM or Boot ROM area. In the CPU rewrite mode, because the
flash memory cannot be read from the CPU, the rewrite control pro-
gram must be transferred to internal RAM area before it can be ex-
ecuted.
Microcomputer Mode and Boot Mode
The control program for CPU rewrite mode must be written into the
user ROM or Boot ROM area in parallel I/O mode beforehand. (If the
control program is written into the Boot ROM area, the standard se-
rial I/O mode becomes unusable.)
See Figure 44 for details about the Boot ROM area.
Normal microcomputer mode is entered when the microcomputer is
reset with pulling CNV
SS
pin low. In this case, the CPU starts operat-
ing using the control program in the user ROM area.
When the microcomputer is reset by pulling the P4
1
/INT
0
pin high,
the CNV
SS
pin high, the CPU starts operating using the control pro-
gram in the Boot ROM area (program start address is FFFC
16
,
FFFD
16
fixation). This mode is called the
“
boot
”
mode.
Block Address
Block addresses refer to the maximum address of each block. These
addresses are used in the block erase command. In case of the
M38507F8, it has only one block.
Outline Performance (CPU Rewrite Mode)
In the CPU rewrite mode, the CPU erases, programs and reads the
internal flash memory as instructed by software commands. This re-
write control program must be transferred to internal RAM before it
can be executed.
The CPU rewrite mode is accessed by applying 5V ± 10% to the
CNV
SS
pin and writing
“
1
”
for the CPU rewrite mode select bit (bit 1
in address 0FFE
16
). Software commands are accepted once the
mode is accessed.
Use software commands to control program and erase operations.
Whether a program or erase operation has terminated normally or in
error can be verified by reading the status register.
Figure 45 shows the flash memory control register.
Bit 0 is the RY/BY status flag used exclusively to read the operating
status of the flash memory. During programming and erase opera-
tions, it is
“
0
”
. Otherwise, it is
“
1
”
.
Bit 1 is the CPU rewrite mode select bit. When this bit is set to
“
1
”
and
5V ± 10% are applied to the CNV
SS
pin, the M38507F8 accesses the
CPU rewrite mode. Software commands are accepted once the
mode is accessed. In CPU rewrite mode, the CPU becomes unable
to access the internal flash memory directly. Therefore, use the con-
trol program in RAM for write to bit 1. To set this bit to
“
1
”
, it is neces-
sary to write
“
0
”
and then write
“
1
”
in succession. The bit can be set
to
“
0
”
by only writing a
“
0
”
.
Bit 2 is the CPU rewrite mode entry flag. This bit can be read to
check whether the CPU rewrite mode has been entered or not.
Bit 3 is the flash memory reset bit used to reset the control circuit of
the internal flash memory. This bit is used when exiting CPU rewrite
mode and when flash memory access has failed. When the CPU
rewrite mode select bit is
“
1
”
, writing
“
1
”
for this bit resets the control
circuit. To release the reset, it is necessary to set this bit to
“
0
”
.
Bit 4 is the User area/Boot area selection bit. When this bit is set to
“
1
”
, Boot ROM area is accessed, and CPU rewrite mode in Boot
ROM area is available. In boot mode, this bit is set
“
1
”
automatically.
Operation of this bit must be in RAM area.
Figure 46 shows a flowchart for setting/releasing the CPU rewrite
mode.
Precautions on CPU Rewrite Mode
Described below are the precautions to be observed when rewriting
the flash memory in CPU rewrite mode.
(1) Operation speed
During CPU rewrite mode, set the internal clock frequency 4MHz
or less using the main clock division ratio selection bits (bit 6, 7 at
003B
16
).
(2) Instructions inhibited against use
The instructions which refer to the internal data of the flash
memory cannot be used during CPU rewrite mode .
(3) Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode be-
cause they refer to the internal data of the flash memory.
(4) Watchdog timer
In case of the watchdog timer has been running already, the in-
ternal reset generated by watchdog timer underflow does not
happen, because of watchdog timer is always clearing during
program or erase operation.
(5) Reset
Reset is always valid. In case of CNV
SS
= H when reset is re-
leased, boot mode is active. So the program starts from the ad-
dress contained in address FFFC
16
and FFFD
16
in boot ROM
area.
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