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| 型號(hào)： | M38503M4H |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 31/86頁(yè) |
| 文件大?。?/td> | 1193K |
| 代理商： | M38503M4H |
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31
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
A-D CONVERTER
[A-D Conversion Registers (ADL, ADH)]
0035
16
, 0036
16
The A-D conversion registers are read-only registers that store the
result of an A-D conversion. Do not read these registers during an
A-D conversion.
[AD Control Register (ADCON)] 0034
16
The AD control register controls the A-D conversion process. Bits
0 to 2 select a specific analog input pin. Bit 4 indicates the
completion of an A-D conversion. The value of this bit remains at
“
0
”
during an A-D conversion and changes to
“
1
”
when an A-D
conversion ends. Writing
“
0
”
to this bit starts the A-D conversion.
Comparison Voltage Generator
The comparison voltage generator divides the voltage between
AV
SS
and V
REF
into 1024 and outputs the divided voltages.
Channel Selector
The channel selector selects one of ports P3
0
/AN
0
to P3
4
/AN
4
and
inputs the voltage to the comparator.
Comparator and Control Circuit
The comparator and control circuit compare an analog input volt-
age with the comparison voltage, and the result is stored in the
A-D conversion registers. When an A-D conversion is completed,
the control circuit sets the A-D conversion completion bit and the
A-D interrupt request bit to
“
1
”
.
Note that because the comparator consists of a capacitor cou-
pling, set f(X
IN
) to 500 kHz or more during an A-D conversion.
When the A-D converter is operated at low-speed mode, f(X
IN
)
and f(X
CIN
) do not have the lower limit of frequency, because of
the A-D converter has a built-in self-oscillation circuit.
Fig. 31 Structure of AD control register
Fig. 32 Structure of A-D conversion registers
Fig. 33 Block diagram of A-D converter
C
h
a
n
n
e
l
s
e
l
e
c
t
o
r
A
-
D
c
o
n
t
r
o
l
c
i
r
c
u
i
t
A-D conversion low-order register
Resistor ladder
V
REF
AV
SS
C
o
m
p
a
r
a
t
o
r
A
-
D
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
b
7
b
0
3
10
P
P
P
P
P
3
0
/
3
1
/
3
2
/
3
3
/
3
4
/
A
A
A
A
A
N
0
N
1
N
2
N
3
N
4
D
a
t
a
b
u
s
A
(A
D
c
d
o
r
n
e
t
s
r
s
o
l
0
r
0
e
g
3
i
s
t
6
)
e
r
A-D conversion high-order register
d
4
1
(Address 0036
16
)
(Address 0035
16
)
A
(
D
A
c
C
o
n
O
t
N
r
o
l
a
r
e
d
g
d
i
r
s
e
t
e
s
r
s
D
:
0
0
3
4
1
6
)
A
n
a
b
l
o
g
b
1
i
n
b
p
0
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
s
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
:
:
:
:
:
P
P
P
P
P
3
0
/
3
1
/
3
2
/
3
3
/
3
4
/
A
A
A
A
A
N
0
N
1
N
2
N
3
N
4
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
A
-
D
c
0
1
o
:
:
n
C
C
v
o
o
e
r
s
v
v
i
e
e
o
r
r
n
s
s
i
i
c
o
o
o
n
n
m
i
c
p
o
l
p
m
e
r
t
o
p
i
o
g
l
e
n
r
e
t
e
b
s
d
i
s
t
n
n
n
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
b
7
b0
2
10-bit reading
(Read address 0036
16
before 0035
16
)
(Address 0036
16
)
(Address 0035
16
)
8-bit reading (Read only address 0035
16
)
(Address 0035
16
)
b8
0
b7 b
6 b5 b
4 b
3 b
2 b
1 b
0
b7
b
0
b9
b
7
b
Note :
The high-order 6 bits of address 0036
16
become
“
0
”
at reading.
b9 b8 b7 b6 b5 b4 b3 b2
b7
b
0
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