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參數(shù)資料
| 型號： | M38503M4H |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 44/86頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | M38503M4H |
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44
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Table 11 Definition of each bit in status register
Status Register
The status register shows the operating state of the flash memory
and whether erase operations and programs ended successfully or
in error. It can be read in the following ways.
(1) By reading an arbitrary address from the user ROM area after
writing the read status register command (70
16
)
(2) By reading an arbitrary address from the user ROM area in the
period from when the program starts or erase operation starts to
when the read array command (FF
16
) is input
Table 11 shows the status register.
Also, the status register can be cleared in the following way.
(1) By writing the clear status register command (50
16
)
(2) In the deep power down mode
(3) In the power supply off state
After a reset, the status register is set to
“
80
16
”
.
Each bit in this register is explained below.
Sequencer status (SR7)
After power-on, and after recover from deep power down mode, the
sequencer status is set to
“
1
”
(ready).
The sequencer status indicates the operating status of the device.
This status bit is set to
“
0
”
(busy) during write or erase operation and
is set to
“
1
”
upon completion of these operations.
Erase status (SR5)
The erase status informs the operating status of erase operation to
the CPU. When an erase error occurs, it is set to
“
1
”
.
The erase status is reset to
“
0
”
when cleared.
Program status (SR4)
The program status informs the operating status of write operation to
the CPU. When a write error occurs, it is set to
“
1
”
.
The program status is reset to
“
0
”
when cleared.
If
“
1
”
is written for any of the SR5 or SR4 bits, the program, erase all
blocks, and block erase commands are not accepted. Before ex-
ecuting these commands, execute the clear status register com-
mand (50
16
) and clear the status register.
Also, any commands are not correct, both SR5 and SR4 are set to
“
1
”
.
Each bit of
SRD0 bits
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Definition
“
1
”
“
0
”
Ready
-
Terminated in error
Terminated in error
-
-
-
-
Sequencer status
Reserved
Erase status
Program status
Reserved
Reserved
Reserved
Reserved
Status name
Busy
-
Terminated normally
Terminated normally
-
-
-
-
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