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參數(shù)資料
| 型號(hào)： | M38503M4H |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 26/86頁 |
| 文件大?。?/td> | 1193K |
| 代理商： | M38503M4H |
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26
3850 Group (Spec. H)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
G
SERIAL I/O2
The serial I/O2 can be operated only as the clock synchronous type.
As a synchronous clock for serial transfer, either internal clock or
external clock can be selected by the serial I/O2 synchronous clock
selection bit (b6) of serial I/O2 control register 1.
The internal clock incorporates a dedicated divider and permits se-
lecting 6 types of clock by the internal synchronous clock selection
bits (b2, b1, b0) of serial I/O2 control register 1.
Regarding S
OUT2
and S
CLK2
being output pins, either CMOS output
format or N-channel open-drain output format can be selected by the
P0
1
/S
OUT2
, P0
2
/S
CLK2
P-channel output disable bit (b7) of
serial I/O2 control register 1.
When the internal clock has been selected, a transfer starts by a
write signal to the serial I/O2 register (address 0017
16
). After comple-
tion of data transfer, the level of the S
OUT2
pin goes to high imped-
ance automatically but bit 7 of the serial I/O2 control register 2 is not
set to
“
1
”
automatically.
When the external clock has been selected, the contents of the serial
I/O2 register is continuously sifted while transfer clocks are input.
Accordingly, control the clock externally. Note that the S
OUT2
pin does
not go to high impedance after completion of data transfer.
To cause the S
OUT2
pin to go to high impedance in the case where
the external clock is selected, set bit 7 of the serial I/O2 control reg-
ister 2 to
“
1
”
when S
CLK2
is
“
H
”
after completion of data transfer. After
the next data transfer is started (the transfer clock falls), bit 7 of the
serial I/O2 control register 2 is set to
“
0
”
and the S
OUT2
pin is put into
the active state.
Regardless of the internal clock to external clock, the interrupt re-
quest bit is set after the number of bits (1 to 8 bits) selected by the
optional transfer bit is transferred. In case of a fractional number of
bits less than 8 bits as the last data, the received data to be stored in
the serial I/O2 register becomes a fractional number of bits close to
MSB if the transfer direction selection bit of serial I/O2 control regis-
ter 1 is LSB first, or a fractional number of bits close to LSB if the said
bit is MSB first. For the remaining bits, the previously received data
is shifted.
At transmit operation using the clock synchronous serial I/O, the S
CMP2
signal can be output by comparing the state of the transmit pin S
OUT2
with the state of the receive pin S
IN2
in synchronization with a rise of
the transfer clock. If the output level of the S
OUT2
pin is equal to the
input level to the S
IN2
pin,
“
L
”
is output from the S
CMP2
pin. If not,
“
H
”
is output. At this time, an INT
2
interrupt request can also be gener-
ated. Select a valid edge by bit 2 of the interrupt edge selection reg-
ister (address 003A
16
).
[Serial I/O2 Control Registers 1, 2 (SIO2CON1 /
SIO2CON2)] 0015
16,
0016
16
The serial I/O2 control registers 1 and 2 are containing various se-
lection bits for serial I/O2 control as shown in Figure 23.
Fig. 23 Structure of Serial I/O2 control registers 1, 2
S
(
S
e
r
O
i
a
2
l
C
I
/
O
O
2
N
1
c
o
:
n
a
t
r
d
o
d
l
r
r
e
e
s
g
s
i
s
0
t
e
0
r
1
5
1
1
6
)
I
S
(
S
e
r
O
i
a
2
l
C
I
/
O
O
2
N
2
c
o
:
n
a
t
r
d
o
d
l
r
r
e
e
s
g
s
i
s
0
t
e
0
r
1
6
1
2
I
6
)
b7 b0
O
b
0
0
0
0
1
1
1
1
p
t
b
0
0
1
1
0
0
1
1
i
1
o
n
b
a
0
0
1
0
1
0
1
0
1
l
t
r
a
n
s
f
e
r
b
i
t
s
2
:
:
:
:
:
:
:
:
1
2
3
4
5
6
7
8
b
b
b
b
b
b
b
b
i
i
i
i
i
i
i
i
t
t
t
t
t
t
t
t
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
"
0
"
w
h
e
n
r
e
a
d
)
S
0
1
e
:
:
r
P
S
C
i
a
4
3
M
l
I
/
I
P
O
/
O
2
2
I
/
O
c
o
m
p
a
r
i
s
o
n
s
i
g
n
a
l
c
o
n
t
r
o
l
b
i
t
o
u
t
p
u
t
S
O
0
:
1
:
U
O
O
T
u
u
2
t
t
p
p
p
i
n
t
t
a
h
c
o
c
i
g
n
t
i
h
t
r
e
-
i
o
l
b
i
t
(
P
0
1
)
u
u
v
m
p
e
d
a
n
c
e
Internal synchronous clock selection bits
b2 b1 b0
0 0 0: f(X
IN
)/8 (f(X
CIN
)/8 in low-speed mode)
0 0 1: f(X
IN
)/16 (f(X
CIN
)/16 in low-speed mode)
0 1 0: f(X
IN
)/32 (f(X
CIN
)/32 in low-speed mode)
0 1 1: f(X
IN
)/64 (f(X
CIN
)/64 in low-speed mode)
1 1 0: f(X
IN
)/128 f(X
CIN
)/128 in low-speed mode)
1 1 1: f(X
IN
)/256 (f(X
CIN
)/256 in low-speed mode)
Serial I/O2 port selection bit
0: I/O port
1: S
OUT2
,S
CLK2
output pin
S
RDY2
output enable bit
0: P0
3
pin is normal I/O pin
1: P0
3
pin is S
RDY2
output pin
Transfer direction selection bit
0: LSB first
1: MSB first
Serial I/O2 synchronous clock selection bit
0: External clock
1: Internal clock
P0
1
/S
OUT2 ,
P0
2
/S
CLK2
P-channel output disable bit
0: CMOS output (in output mode)
1: N-channel open-drain output (in output mode )
b
7
b
0
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