參數(shù)資料
型號: M37702M2A
廠商: Mitsubishi Electric Corporation
英文描述: Single Chip 16 Bits CMOS Microcomputer(16位單片機)
中文描述: 單片微機16位的CMOS(16位單片機)
文件頁數(shù): 44/59頁
文件大?。?/td> 811K
代理商: M37702M2A
44
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
CLOCK GENERATING CIRCUIT
Figure 55 shows a block diagram of the clock generator.
When an STP instruction is executed, the internal clock
φ
stops
oscillating at “L” level. At the same time, FFF
16
is written to watch-
dog timer and the watchdog timer input connection is forced to f
32
.
This connection is broken and connected to the input determined
by the watchdog timer frequency selection flag when the most sig-
nificant bit of the watchdog timer is cleared or reset.
Oscillation resumes when an interrupt is received, but the internal
clock
φ
remains at “L” level until the most significant bit of the
watchdog timer is cleared. This is to avoid the unstable interval at
the start of oscillation when using a ceramic resonator.
When a WIT instruction is executed, the internal clock
φ
stops at
“L” level, but the oscillator does not stop. The clock is restarted
when an interrupt is received. Instructions can be executed imme-
diately because the oscillator is not stopped.
The stop or wait state is released when an interrupt is received or
when reset is issued. Therefore, interrupts must be enabled be-
fore executing a STP or WIT instruction.
Figure 56 shows a circuit example using a ceramic (or quartz crys-
tal) resonator. Use the manufacture’s recommended values for
constants such as capacitance which differ for each resonator.
Figure 57 shows an example of using an external clock signal.
Fig. 56 Circuit using a ceramic resonator
Fig. 57 External clock input circuit
Fig. 55 Block diagram of a clock generator
1M
Rd
X
IN
X
OUT
M37702M2AXXXFP
30
29
X
IN
X
OUT
Open
External clock source
Vcc
Vss
30
M37702M2AXXXFP
29
X
OUT
X
IN
Watchdog
timer
Interrupt request
WIT instruction
Q
S
R
Q
S
R
STP instruction
STP instruction
Reset
Q
S
R
Internal clock
φ
f
2
f
16
f
32
f
64
f
512
1/2
1/8
1/2
1/2
1/8
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