參數(shù)資料
型號(hào): M37702M2A
廠商: Mitsubishi Electric Corporation
英文描述: Single Chip 16 Bits CMOS Microcomputer(16位單片機(jī))
中文描述: 單片微機(jī)16位的CMOS(16位單片機(jī))
文件頁(yè)數(shù): 27/59頁(yè)
文件大?。?/td> 811K
代理商: M37702M2A
27
MITSUBISHI MICROCOMPUTERS
M37702M2AXXXFP, M37702M2BXXXFP
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Fig. 33 Serial I/O port block diagram
SERIAL I/O PORTS
Two independent serial I/O ports are provided. Figure 33 shows a
block diagram of the serial I/O ports.
Bits 0, 1, and 2 of the UARTi (i = 0, 1) Transmit/Receive mode reg-
ister shown in Figure 34 are used to determine whether to use port
P8 as parallel port, clock synchronous serial I/O port, or asynchro-
nous (UART) serial I/O port using start and stop bits.
Figures 35 and 36 show the connections of receiver/transmitter
according to the mode.
Figure 37 shows the bit configuration of the UARTi transmit/re-
ceive control register.
Each communication method is described below.
Fig. 34 UART i Transmit/ Receive mode register bit
configuration
Data bus (odd)
Data bus (even)
0
0
0
0
0
0
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
8
Receive register
Receive
UART0 (37
16
, 36
16
)
UART1 (3F
16
, 3E
16
)
Reccircuit
RxDi
Data bus (even)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
8
Transmission register
UART0 (33
16
, 32
16
)
UART1 (3B
16
, 3A
16
)
control circuit
Transmission
f
2
f
16
f
64
f
512
CLKi
CTSi/RTSi
1/16 Divider
UART receive
Clock synchronous
UART transmission
1/16 Divider
Clock synchronous
Clock synchronous
(Internal clock)
1/2 Divider
Clock synchronous
(External clock)
Divider
External
Internal
Clock source selection
Bit rate
UART0(31
16
)
UART1(39
16
)
Receive clock
Transmission clock
Data bus (odd)
TxDi
Clock s(Internal clock)
UART 0 transmit/receive mode register 30
16
UART 1 transmit/receive mode register 38
16
Serial communication method selection bits
0 0 0 : Parallel port
0 0 1 : Clock synchronous
1 0 0 : 7-bit UART
1 0 1 : 8-bit UART
1 1 0 : 9-bit UART
Internal clock/External clock selection bit
0 : Internal clock
1 : External clock
Stop bit length selection bit
0 : 1 stop bit
1 : 2 stop bits
Even/Odd parity selection bit
0 : Odd parity
1 : Even parity
Parity enable selection bit
0 : No parity
1 : With parity
Sleep selection bit
0 : No sleep
1 : Sleep
Addresses
7 6 5 4 3 2 1 0
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