參數(shù)資料
型號(hào)： M37643F8HP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù)： 82/123頁
文件大?。?/td> 1292K
代理商： M37643F8HP
Rev.2.00
Aug 28, 2006
page 59 of 119
7643 Group
REJ03B0054-0200
X : Not fixed
Notes1: When using the endpoint 1, this contents are “0116”.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
(37)
(38)
(39)
(40)
(41)
(42)
(43)
(44)
(45)
(46)
(47)
(48)
(49)
(50)
(51)
(52)
(53)
(54)
(55)
(56)
(57)
(58)
(59)
(60)
(61)
(62)
(63)
(64)
(65)
(66)
(67)
(68)
(69)
(70)
(71)
Register contents
003216
003316
003616
003F16
004016
004116
004216
004316
004416
004516
004616
004716
005016
005116
005216
005316
005416
005516
005816
005916
005A16
005B16
005C16
005D16
005F16
006A16
006C16
006D16
006E16
006F16
FFC916
(PS)
(PCH)
(PCL)
Address
0016
FF16
AddressRegister contents
0016
FF16
0016
FFFB16 contents
FFFA16 contents
CPU mode register A (CPUA)
CPU mode register B (CPUB)
Interrupt request register A (IREQA)
Interrupt request register B (IREQB)
Interrupt request register C (IREQC)
Interrupt control register A (ICONA)
Interrupt control register B (ICONB)
Interrupt control register C (ICONC)
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Port control register (PTC)
Interrupt polarity select register (IPOL)
Port P2 pull-up control register (PUP2)
USB control register (USBC)
Port P6 (P6)
Port P6 direction register (P6D)
Port P5 (P5)
Port P5 direction register (P5D)
Port P4 (P4)
Port P4 direction register (P4D)
Port P7 (P7)
Port P7 direction register (P7D)
Port P8 (P8)
Port P8 direction register (P8D)
Clock control register (CCR)
Timer 1 (T1)
Timer 2 (T2)
Timer 3 (T3)
Timer 123 mode register (T123M)
Serial I/O control register 1 (SIOCON1)
Serial I/O control register 2 (SIOCON2)
UART mode register (UMOD)
000016
000116
000216
000316
000416
000516
000616
000716
000816
000916
000A16
000B16
000C16
000D16
000E16
000F16
001016
001116
001216
001316
001416
001516
001616
001716
001816
001916
001A16
001B16
001C16
001D16
001F16
002416
002516
002616
002916
002B16
002C16
003016
1
0000 0
0
UART status register (USTS)
UART control register (UCON)
UART RTS control register (URTSC)
DMAC index and status register (DMAIS)
DMAC channel x mode register 1 (DMAx1)
DMAC channel x mode register 2 (DMAx2)
DMAC channel x source register Low (DMAxSL)
DMAC channel x source register High (DMAxSH)
DMAC channel x destination register Low (DMAxDL)
DMAC channel x destination register
High (DMAxDH)
DMAC channel x transfer count register Low (DMAxCL)
DMAC channel x transfer count register High (DMAxCH)
USB address register (USBA)
USB power management register (USBPM)
USB interrupt status register 1 (USBIS1)
USB interrupt status register 2 (USBIS2)
USB interrupt enable register 1 (USBIE1)
USB interrupt enable register 2 (USBIE2)
USB endpoint index register (USBINDEX)
USB endpoint x IN control register (IN_CSR)
USB endpoint x OUT control register (OUT_CSR)
USB endpoint x IN max. packet size register (IN_MAXP)
USB endpoint x OUT max. packet size register (OUT_MAXP)
USB endpoint x OUT write count register (WRT_CNT)
USB endpoint FIFO mode register (USBFIFOMR)
Flash memory control register (FMCR)
Frequency synthesizer control register (FSC)
Frequency synthesizer multiply register 1 (FSM1)
Frequency synthesizer multiply register 2 (FSM2)
Frequency synthesizer divide register (FSM2)
ROM code protect control register (ROMCP)
Processor status register
Program counter
00
11
00
01 1
00
10 0
1
10000 0 0 0
01 00
0
01 0
00 0
0
01 0
00 0
0
0000 0
01
0
00 0
01
0
10
1
00
0
10 0
00
01
(Note 1)
(Note 3)
3: The flash memory control register and the ROM code protect control register exists in the flash memory version only.
2: Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set.
00
0
00
1
00
1
111 1
1
Fig. 55 Internal status at reset
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