參數(shù)資料
型號： M37643F8HP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80
封裝： 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80
文件頁數(shù)： 70/123頁
文件大?。?/td> 1292K
代理商： M37643F8HP
Rev.2.00
Aug 28, 2006
page 48 of 119
7643 Group
REJ03B0054-0200
Fig. 39 Structure of USB interrupt status register 2
USB interrupt status register 2 (address 005316)
USBIS2
Reserved bit (“0” at read/write)
USB reset interrupt status flag (INTST13)
0: Except the following condition
1: Set at receiving of USB reset signal
USB resume signal interrupt status flag (INTST14)
0: Except the following condition
1: Set at receiving of resume signal
USB suspend signal interrupt status flag (INTST15)
0: Except the following condition
1: Set at receiving of suspend signal
b0
b7
0000
0
[USB Interrupt Enable Registers 1 and 2] USBIE1, USBIE2
The USB interrupt enable registers are used to enable the USB
USB interrupt enable register 1 (address 005416)
USBIE1
USB endpoint 0 interrupt enable bit (INTEN0)
0: Disabled
1: Enabled
Reserved bit (“0” at read/write)
USB endpoint 1 IN interrupt enable bit (INTEN2)
0: Disabled
1: Enabled
USB endpoint 1 OUT interrupt enable bit (INTEN3)
0: Disabled
1: Enabled
USB endpoint 2 IN interrupt enable bit (INTEN4)
0: Disabled
1: Enabled
USB endpoint 2 OUT interrupt enable bit (INTEN5)
0: Disabled
1: Enabled
Reserved bit (Undefined at read/“0” at write)
b0
b7
0
function interrupt. Upon reset, all USB interrupts except the USB
suspend and USB resume interrupts are enabled.
Fig. 40 Structure of USB interrupt enable register 1
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