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| 型號(hào)： | M37643F8HP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁(yè)數(shù)： | 63/123頁(yè) |
| 文件大?。?/td> | 1292K |
| 代理商： | M37643F8HP |
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Rev.2.00
Aug 28, 2006
page 42 of 119
7643 Group
REJ03B0054-0200
USB Transmission
Endpoint 0 to Endpoint 2 have IN (transmit) FIFOs individually.
Each endpoint’s FIFO is configured in following way:
Endpoint 0: 16-byte
Endpoint 1: 128-byte
Endpoint 2: Mode 0: 32-byte
Mode 1: 128-byte
When Endpoint 2 is used for data transmit, the IN FIFO size can
be selected. Endpoint 2 have 2 modes programmable IN-FIFO.
Each mode can be selected by the USB endpoint FIFO mode se-
lection register (address 005F16).
When writing data to the USB Endpoint-x FIFO (addresses 006016
to 006216) in the SFR area, the internal write pointer for the IN
FIFO is automatically increased by 1. When the AUTO_SET bit is
“1” and if the stored data reaches to the max. packet value set in
USB Endpoint x IN max. packet size register (address 005B16),
the USB FCU sets the IN_PKT_RDY bit to “1”. When the
AUTO_SET bit is “0”, the IN_PKT_RDY bit will not be automati-
cally set to “1”; it must be set to “1” by software. (The AUTO_SET
bit function is not applicable to Endpoint 0.)
The USB FCU transmits the data when it receives the next IN to-
ken. The IN_PKT_RDY bit automatically goes to “0” when the data
transfer is complete.
qInterrupt transfer mode
Endpoints 1 to 2 can be used in interrupt transfer mode. During a
regular interrupt transfer, an interrupt transaction is similar to the
bulk transfer. Therefore, there is no special setting required. When
IN-endpoint is used for a rate feedback interrupt transfer, INTPT
bit of the IN_CSR register must be set to “1”. The following steps
show how to configure the IN-endpoint for the rate feedback inter-
rupt transfer.
1. Set a value which is larger than 1/2 of the USB Endpoint-x FIFO
size to the USB Endpoint x IN max. package size register.
2. Set INTPT bit to “1”.
3. Flush the old data in the FIFO.
4. Store transmission data to the IN FIFO and set the
IN_PKT_RDY bit to “1”.
5. Repeat steps 3 and 4.
In a real application, the function-side always has transfer data
when the function sends an endpoint in a rate feedback interrupt.
Accordingly, the USB FCU never returns a NAK against the host
IN token for the rate feedback interrupt. The USB FCU always
transmits data in the FIFO in response to an IN token, regardless
of IN_PKT_RDY. However, this premises that there is always an
ACK response from Host PC after the 7643 Group has transmitted
data to IN token.
When MAXP size
≤ (a half of IN FIFO size), the IN FIFO can store
two packets (called double buffer). At this time, the IN FIFO sta-
tus can be checked by monitoring the IN_PKT_RDY bit and the
TX_NOT_EPT flag. The TX_NOT_EPT flag is a read-only flag
which shows the FIFO state. When IN_PKY_RDY = 0 and
TX_NOT_EPT = 0, IN FIFO is empty. When IN_PKY_RDY = 0 and
TX_NOT_EPT = 1, IN FIFO has one packet.
In double buffer mode, as long as the IN FIFO is not filled with
double packets, IN_PKT_RDY will not be set to “1”, even if it is set
to “1” by software, but TX_NOT_EPT flag will be set to “1”. In
single buffer mode, if MAXP > (a half of IN FIFO), this condition
never occurs.
When IN_PKT_RDY = “1” and TX_NOT_EPT = “1”, IN FIFO holds
two packets in double buffer mode and one packet in single
packet mode. In single packet mode, when the IN_PKT_RDY bit is
set to “1” by software, the TX_NOT_EPT flag is set to “1” as well.
During double buffer mode, if you want to load two packets se-
quentially, you must set the IN_PKT_RDY bit to “1” each time a
packet is loaded.
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