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參數(shù)資料
| 型號(hào)： | M37643F8HP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 74/123頁 |
| 文件大小： | 1292K |
| 代理商： | M37643F8HP |
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Rev.2.00
Aug 28, 2006
page 52 of 119
7643 Group
REJ03B0054-0200
[USB Endpoint x (x = 1, 2) OUT Control Register] OUT_CSR
This register contains the information and status of the respective
OUT endpoints 1, 2. In the endpoint 0, all bits are reserved and
cannot be used (they will all be read out as “0”). The USB FCU
sets the OUT_PKT_RDY flag to “1” after a data packet has been
received into the OUT FIFO. After reading the data packet in the
OUT FIFO, clear this flag to “0”. However, if there is still data in the
OUT FIFO, the flag cannot be cleared even by writing “0” by soft-
ware.
Fig. 45 Structure of USB endpoint x (x = 1, 2) OUT control register
USB endpoint x OUT control register (address 005A16)
OUT_CSR
OUT_PKT_RDY flag (OUTXCSR0)
0: Except the following condition (Note 3)
1: End of a data packet reception (Note 2)
Reserved bit (“0” at read/write)
SEND_STALL bit (OUTXCSR2) (Note 2)
0: Except the following condition
1: Transmitting STALL handshake signal
TOGGLE_INIT bit (OUTXCSR3) (Note 2)
0: Except the following condition
1: Initializing the data toggle sequence bit
FORCE_STALL flag (OUTXCSR4)
0: Except the following condition (Note 2)
1: Protocol error detected (Note 1)
Reserved bit (“0” at read/write)
FLUSH bit (OUTXCSR6)
0: Except the following condition (Note 4)
1: Flush FIFO. (Note 4)
AUTO_CLR bit (OUTXCSR7) (Note 2)
0: AUTO_CLR disabled
1: AUTO_CLR enabled
b0
b7
0
Notes 1: This bit is automatically set to “1” or cleared to “0”.
2: The user must program to “1” or “0”.
3: When AUTO_SET bit is “0”, the user must set to “1”.
When AUTO_SET bit is “1”, this bit is automatically set to “1”.
4: This bit is automatically cleared to “0” after setting “1”.
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