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參數資料
| 型號： | M37643F8FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁數： | 34/120頁 |
| 文件大?。?/td> | 1253K |
| 代理商： | M37643F8FP |
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20
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7643 Group
PRELIMINAR
Y
Notice:
This
is not
a final
specification.
Some
parametric
limits
are
subject
to
change.
INTERRUPTS
There are fourteen interrupt sources: three externals, ten internals,
and one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt has both an Inter-
rupt Request Bit and an Interrupt Enable Bit, and is controlled by the
Interrupt Disable Flag (I). An interrupt occurs if the corresponding
Interrupt Request and Enable Bits are “1” and the Interrupt Disable
Flag is “0”.
Interrupt Enable Bits can be set or cleared by software. Interrupt Re-
quest Bits can be cleared by software, but cannot be set by software.
Additionally, an active edge of INT0 and INT1 can be selected by
using the interrupt polarity select register (address 001116).
The BRK instruction interrupt and reset cannot be disabled with any
flag or bit. The I Flag disables all interrupts except the BRK instruc-
tion interrupt and reset. If several interrupts requests occur at the
same time, the interrupt with the highest priority is accepted first.
Interrupt Operation
When an interrupt request occurs, the following operations are auto-
matically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack.
3. The Interrupt Disable Flag is set and the corresponding in-
terrupt request bit is cleared.
4. The interrupt jump destination address is read from the vector
table into the program counter.
sNotes
When setting the followings, the interrupt request bit may be set to
“1”.
When setting external interrupt active edge
Related register: Interrupt polarity select register (address 001116)
When not requiring for the interrupt occurrence synchronized with
these setting, take the following sequence.
Set the corresponding Interrupt Enable Bit to “0” (disabled).
Set the Interrupt Polarity Select Bit (Active Edge Switch Bit).
Set the corresponding Interrupt Request Bit to “0” after 1 or more
instructions have been executed.
Set the corresponding Interrupt Enable Bit to “1” (enabled).
Fig. 16 Interrupt control
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
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相關代理商/技術參數 |
參數描述 |
|---|---|
| M37643F8M8-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37643M8E8-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37643M8M8-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M3764A-12 | 制造商:OK International 功能描述: |
| M3765 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:HORN/SIREN WITH SOFT CHIRP 6 ALARM SOUNDS |
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