參數(shù)資料
型號: M37641M8-XXXFP
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP80
封裝: 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁數(shù): 84/136頁
文件大?。?/td> 1672K
代理商: M37641M8-XXXFP
51
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
[USB Interrupt Enable Registers 1 and 2] USBIE1, USBIE2
The USB interrupt enable registers are used to enable the USB
USB interrupt enable register 1 (address 005416)
USBIE1
USB endpoint 0 interrupt enable bit (INTEN0)
0: Disabled
1: Enabled
Reserved bit (“0” at read/write)
USB endpoint 1 IN interrupt enable bit (INTEN2)
0: Disabled
1: Enabled
USB endpoint 1 OUT interrupt enable bit (INTEN3)
0: Disabled
1: Enabled
USB endpoint 2 IN interrupt enable bit (INTEN4)
0: Disabled
1: Enabled
USB endpoint 2 OUT interrupt enable bit (INTEN5)
0: Disabled
1: Enabled
USB endpoint 3 IN interrupt enable bit (INTEN6)
0: Disabled
1: Enabled
USB endpoint 3 OUT interrupt enable bit (INTEN7)
0: Disabled
1: Enabled
b0
b7
0
USB interrupt enable register 2 (address 005516)
USBIE2
USB endpoint 4 IN interrupt enable bit (INTEN8)
0: Disabled
1: Enabled
USB endpoint 4 OUT interrupt enable bit (INTEN9)
0: Disabled
1: Enabled
Reserved bit (“0” at read/write)
USB overrun/underrun interrupt enable bit (INTEN12)
0: Disabled
1: Enabled
Reserved bit (“1” at read/write)
Reserved bit (“0” at read/write)
USB suspend/resume interrupt enable bit (INTEN15)
0: Disabled
1: Enabled
b0
b7
00
01
function interrupt. Upon reset, all USB interrupts except the USB
suspend and USB resume interrupts are enabled.
Fig. 42 Structure of USB interrupt enable register 1
Fig. 43 Structure of USB interrupt enable register 2
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