85
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
7641 Group
Reset input “L” pulse width
Main clock input cycle time (Note)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub-clock input cycle time
Sub-clock input “H” pulse width
Sub-clock input “L” pulse width
INT0, INT1 input cycle time
INT0, INT1 input “H” pulse width
INT0, INT1 input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
Timer TOUT delay time
Timer CNTR0 delay time (Pulse output mode)
Timer CNTR0 input cycle time (Event counter mode)
Timer CNTR0 input “H” pulse width (Event counter mode)
Timer CNTR0 input “L” pulse width (Event counter mode)
Timer CNTR1 delay time (Pulse output mode)
Timer CNTR1 input cycle time (Event counter mode)
Timer CNTR1 input “H” pulse width (Event counter mode)
Timer CNTR1 input “L” pulse width (Event counter mode)
Serial I/O external clock input cycle time
Serial I/O external clock input “H” pulse width
Serial I/O external clock input “L” pulse width
Serial I/O input setup time (external clock)
Serial I/O input hold time (external clock)
Serial I/O output delay time (external clock)
Serial I/O SRDY valid time (external clock)
Serial I/O internal clock output cycle time
Serial I/O internal clock output “H” pulse width
Serial I/O internal clock output “L” pulse width
Serial I/O input setup time (internal clock)
Serial I/O input hold time (internal clock)
Serial I/O output delay time (internal clock)
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(XCIN)
tWH(XCIN)
tWL(XCIN)
tC(INT)
tWH(INT)
tWL(INT)
tC(CNTRI)
tWH(CNTRI)
tWL(CNTRI)
td(
φ -TOUT)
td(
φ -CNTR0)
tC(CNTRE0)
tWH(CNTRE0)
tWL(CNTRE0)
td(
φ -CNTR1)
tC(CNTRE1)
tWH(CNTRE1)
tWL(CNTRE1)
tC(SCLKE)
tWH(SCLKE)
tWL(SCLKE)
tsu(SRXD-SCLKE)
th(SCLKE-SRXD)
td(SCLKE-STXD)
tv(SCLKE-SRDY)
tc(SCLKI)
tWH(SCLKI)
tWL(SCLKI)
tsu(SRXD-SCLKI)
th(SCLKI-SRXD)
td(SCLKI-STXD)
Limits
s
ns
Parameter
Min.
2
41.66
0.4tc(XIN)
200
0.4tc(XCIN)
200
90
200
80
200
0.4tc(CNTRE0)
200
0.4tc(CNTRE1)
400
190
180
15
10
166.66
0.5tc(SCLKI) – 5
20
5
Typ.
Max.
Symbol
Unit
Table 14 Timing requirements (Vcc = 4.15 to 5.25 V, Vss = 0 V, Ta = –20 to 70°C, unless otherwise noted)
Note: Make sure not to exceed 12 MHz of
φ, in other words, tc(φ) ≥ 83.33 ns). For example, set bit 7 of the clock control register (CCR) to “0” in the case of
tc(XIN)
< 41.66 ns.
Timing Requirements
In Vcc = 5 V
15
25
26
5