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| 型號(hào)： | M37641M8-XXXFP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80 |
| 文件頁(yè)數(shù)： | 77/136頁(yè) |
| 文件大?。?/td> | 1672K |
| 代理商： | M37641M8-XXXFP |
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45
7641 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
USB Reception
Endpoint 0 to Endpoint 4 have OUT (receive) FIFOs individually.
Each endpoint’s FIFO is configured in following way:
Endpoint 0: 16-byte
Endpoint 1: Mode 0: 800-byte
Mode 1: 1024-byte
Mode 2: 2048-byte
Mode 3: 0-byte
Mode 4: 1280-byte
Mode 5: 1168-byte
Endpoint 2: Mode 0: 32-byte
Mode 1: 128-byte
Endpoint 3: 16-byte
Endpoint 4: 16-byte
When Endpoint 1 or Endpoint 2 is used for data receive, the OUT
FIFO size can be selected. Endpoint 1 and Endpoint 2 have pro-
grammable IN-FIFOs size; 6 modes for Endpoint 1, and 2 modes
for Endpoint 2. Each mode can be selected by the USB endpoint
FIFO mode selection register (address 005F16).
Data transmitted from the host-PC is stored in Endpoint x FIFO
(006016 to 006416). Every time the data is stored in the FIFO, the
internal OUT FIFO write pointer is increased by 1. When one com-
plete data packet is stored, the OUT_PKT_RDY flag is set to “1”
and the number of received data packets is stored in USB End-
point x OUT write count registers (Low and High). When the
AUTO_CLR bit is “1” and the received data is read out from the
OUT FIFO, the OUT_PKT_RDY flag is cleared to “0”. When the
AUTO_CLR bit is “1”, the OUT_PKT_RDY flag will not be cleared
automatically by the FIFO read; it must be cleared by software.
(The AUTO-CLR bit function is not applicable in Endpoint 0.)
When MAXP size
≤ (a half of OUT FIFO size), the OUT_FIFO can
receive 2 packets (double buffer). At this time, the OUT_ FIFO sta-
tus can be checked by the OUT_PKT_RDY flag. When the FIFO
holds two packets and one packet is read from the FIFO, the
OUT_PKT_RDY flag is not cleared even if it is set to “0”. (The flag
returns from “0” to “1” in one
φ cycle after the read-out). During
double buffer mode, the USB Endpoint x OUT write count regis-
ters (Low and High) holds the number of previously received
packets. This count register is updated after reading out one of
packets in the OUT FIFO and clearing the OUT_PKT_RDY flag to
“0”.
TOGGLE Initialization
In order to initialize the data toggle sequence bit of the endpoint,
in other words, resetting the next data packet to DATA0; set the
ISO/TOGGLE_INT bit to “1” and then clear back to “0”.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M37643M8-XXXFP | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80 |
| M37643F8HP | 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80 |
| M37643M8-XXXHP | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP80 |
| M37700M2-XXXFP | 16-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP80 |
| M37701M2-001SP | 16-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP64 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M37641M8-XXXHP | 制造商:MITSUBISHI 制造商全稱(chēng):Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M376420RS | 制造商:OKI 功能描述:3764-20 NOTES |
| M3764-20RS | 制造商:OKI 功能描述:3764-20 NOTES 制造商: 功能描述:Dynamic RAM, Page Mode, 64K x 1, 16 Pin, Plastic, DIP 制造商:OK International 功能描述:Dynamic RAM, Page Mode, 64K x 1, 16 Pin, Plastic, DIP |
| M3-7643A-S | 制造商:Harris Corporation 功能描述: |
| M37643F8E8-XXXFP | 制造商:RENESAS 制造商全稱(chēng):Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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